DWC_pcie_wire_cpcie_usp_4x8.csr/project/jenkins/workspace/Esperanto_DV/soc_hal/esperanto-soc/dv/common/scripts/semifore_css/etsoc_esr.cssPE0_DWC_pcie_ctl_AXI_SlaveaddressmapPE0_DWC_pcie_ctl_AXI_SlavePE0_DWC_pcie_ctl_AXI_SlaveDWC_pcie_wire_cpcie_usp_4x8.csr24547R/WPE0_DWC_pcie_ctl_AXI_SlaveDWC PCIE-EP Memory MapgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDRgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_PM_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_LTR_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_LNR_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAPgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC0x00xCFFPE0_DWC_pcie_ctl_AXI_SlavePE0_DWC_pcie_ctl_AXI_Slave0x00x3FPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDRPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR0x00x0PE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REG0x40x4PE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REG0x80x8PE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_IDPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_ID0xC0xCPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG0x100x10PE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR0_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR0_REG0x140x14PE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR1_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR1_REG0x180x18PE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR2_REG0x1C0x1CPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR3_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR3_REG0x200x20PE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR4_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR4_REG0x240x24PE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR5_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR5_REG0x280x28PE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REG0x2C0x2CPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG0x300x30PE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REG0x340x34PE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REG0x380x3B0x3C0x3CPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG0x400x47PE0_DWC_pcie_ctl_AXI_Slave.PF0_PM_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_PM_CAP0x400x40PE0_DWC_pcie_ctl_AXI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REG0x440x44PE0_DWC_pcie_ctl_AXI_Slave.PF0_PM_CAP.CON_STATUS_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PM_CAP.CON_STATUS_REG0x480x4F0x500x67PE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP0x500x50PE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REG0x540x54PE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REG0x580x58PE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REG0x5C0x5CPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REG0x600x60PE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REG0x640x64PE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REG0x680x6F0x700xABPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP0x700x70PE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG0x740x74PE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REG0x780x78PE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUS0x7C0x7CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REG0x800x80PE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REG0x840x930x940x94PE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REG0x980x98PE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REG0x9C0x9CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REG0xA00xA0PE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REG0xA40xAB0xAC0xAF0xB00xBCPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAP0xB00xB0PE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REG0xB40xB4PE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REG0xB80xB8PE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REG0xBC0xBC0xBD0xFF0x1000x147PE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP0x1000x100PE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFF0x1040x104PE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFF0x1080x108PE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFF0x10C0x10CPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFF0x1100x110PE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFF0x1140x114PE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFF0x1180x118PE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFF0x11C0x11CPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_0_OFF0x1200x120PE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_1_OFF0x1240x124PE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_2_OFF0x1280x128PE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_3_OFF0x12C0x1370x1380x138PE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFF0x13C0x13CPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFF0x1400x140PE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFF0x1440x144PE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFF0x1480x197PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP0x1480x148PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_BASEPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_BASE0x14C0x14CPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_10x1500x150PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_20x1540x154PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REG0x1580x158PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC00x15C0x15CPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC00x1600x160PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC00x1640x164PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC10x1680x168PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC10x16C0x16CPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC10x1700x170PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC20x1740x174PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC20x1780x178PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC20x17C0x17CPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC30x1800x180PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC30x1840x184PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3PE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC30x1880x1970x1980x1B7PE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP0x1980x198PE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REG0x19C0x19CPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REG0x1A00x1A0PE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REG0x1A40x1A4PE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REG0x1A80x1A8PE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REG0x1AC0x1ACPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REG0x1B00x1B0PE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REG0x1B40x1B70x1B80x1DFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP0x1B80x1B8PE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REG0x1BC0x1BCPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REG0x1C00x1C0PE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REG0x1C40x1C4PE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REG0x1C80x1C8PE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REG0x1CC0x1CCPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REG0x1D00x1D0PE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REG0x1D40x1D70x1D80x1D8PE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REG0x1DC0x1DCPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REG0x1E00x207PE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP0x1E00x1E0PE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REG0x1E40x1E4PE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REG0x1E80x1E8PE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REG0x1EC0x1ECPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REG0x1F00x1F0PE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REG0x1F40x1F4PE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REG0x1F80x1F8PE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REG0x1FC0x1FCPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REG0x2000x200PE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REG0x2040x204PE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REG0x2080x293PE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP0x2080x208PE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REG0x20C0x20CPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REG0x2100x210PE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REG0x2140x214PE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0PE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_00x2180x2930x2940x29BPE0_DWC_pcie_ctl_AXI_Slave.PF0_LTR_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_LTR_CAP0x2940x294PE0_DWC_pcie_ctl_AXI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REG0x2980x298PE0_DWC_pcie_ctl_AXI_Slave.PF0_LTR_CAP.LTR_LATENCY_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_LTR_CAP.LTR_LATENCY_REG0x29C0x2ABPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP0x29C0x29CPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REG0x2A00x2A0PE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REG0x2A40x2A4PE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REG0x2A80x2A8PE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REG0x2AC0x2BB0x2BC0x2C3PE0_DWC_pcie_ctl_AXI_Slave.PF0_LNR_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_LNR_CAP0x2BC0x2BCPE0_DWC_pcie_ctl_AXI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFF0x2C00x2C0PE0_DWC_pcie_ctl_AXI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFF0x2C40x3C3PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP0x2C40x2C4PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REG0x2C80x2C8PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REG0x2CC0x2CCPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REG0x2D00x2D0PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REG0x2D40x2D4PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REG0x2D80x2D8PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REG0x2DC0x2DCPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REG0x2E00x2F30x2F40x2F4PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REG0x2F80x2F8PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REG0x2FC0x2FCPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REG0x3000x300PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REG0x3040x304PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REG0x3080x308PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REG0x30C0x30CPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REG0x3100x310PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REG0x3140x314PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REG0x3180x318PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REG0x31C0x31CPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REG0x3200x320PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REG0x3240x324PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REG0x3280x328PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REG0x32C0x32CPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REG0x3300x330PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REG0x3340x334PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REG0x3380x338PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REG0x33C0x33CPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REG0x3400x340PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REG0x3440x344PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REG0x3480x348PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REG0x34C0x34CPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REG0x3500x350PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REG0x3540x3630x3640x364PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REG0x3680x368PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REG0x36C0x3730x3740x374PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REG0x3780x378PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REG0x37C0x37CPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REG0x3800x380PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REG0x3840x384PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REG0x3880x388PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REG0x38C0x3930x3940x394PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REG0x3980x398PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REG0x39C0x39CPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REG0x3A00x3A30x3A40x3A4PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REG0x3A80x3A8PE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REG0x3AC0x3ACPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REG0x3B00x3C30x3C40x3FBPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP0x3C40x3C4PE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFF0x3C80x3C8PE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFF0x3CC0x3CCPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFF0x3D00x3D0PE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFF0x3D40x3D4PE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFF0x3D80x3D8PE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFF0x3DC0x3DCPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFF0x3E00x3E0PE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFF0x3E40x3E4PE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFF0x3E80x3E8PE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFF0x3EC0x3ECPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFF0x3F00x3F0PE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFF0x3F40x3F4PE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFF0x3F80x3F8PE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFF0x3FC0x407PE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAP0x3FC0x3FCPE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFF0x4000x400PE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFF0x4040x404PE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFF0x4080x43BPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAP0x4080x408PE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REG0x40C0x40CPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REG0x4100x410PE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REG0x4140x43B0x43C0x4470x4480x47BPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAPPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP0x4480x448PE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REG0x44C0x44CPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REG0x4500x450PE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REG0x4540x454PE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REG0x4580x458PE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REG0x45C0x45CPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REG0x4600x460PE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REGPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REG0x4640x47B0x47C0x6FF0x7000xCFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGICPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC0x7000x700PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFF0x7040x704PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFF0x7080x708PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFF0x70C0x70CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFF0x7100x710PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFF0x7140x714PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFF0x7180x718PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFF0x71C0x71CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFF0x7200x720PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFF0x7240x724PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF0x7280x728PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFF0x72C0x72CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFF0x7300x730PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFF0x7340x734PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFF0x7380x738PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFF0x73C0x73CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFF0x7400x740PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFF0x7440x744PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFF0x7480x748PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFF0x74C0x74CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFF0x7500x750PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFF0x7540x754PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFF0x7580x758PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFF0x75C0x75CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFF0x7600x760PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFF0x7640x764PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFF0x7680x768PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFF0x76C0x76CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFF0x7700x770PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFF0x7740x774PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFF0x7780x80B0x80C0x80CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFF0x8100x810PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFF0x8140x814PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFF0x8180x81B0x81C0x81CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFF0x8200x820PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFF0x8240x824PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFF0x8280x828PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFF0x82C0x82CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFF0x8300x830PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFF0x8340x834PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFF0x8380x838PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFF0x83C0x83CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFF0x8400x840PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFF0x8440x844PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFF0x8480x848PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFF0x84C0x84CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFF0x8500x850PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFF0x8540x854PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFF0x8580x858PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFF0x85C0x85CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFF0x8600x860PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFF0x8640x864PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFF0x8680x868PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFF0x86C0x86CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFF0x8700x870PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFF0x8740x874PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFF0x8780x878PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFF0x87C0x87CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFF0x8800x880PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFF0x8840x884PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFF0x8880x888PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFF0x88C0x88CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFF0x8900x890PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFF0x8940x8A70x8A80x8A8PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFF0x8AC0x8ACPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFF0x8B00x8B30x8B40x8B4PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFF0x8B80x8B8PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFF0x8BC0x8BCPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFF0x8C00x8C0PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFF0x8C40x8C4PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFF0x8C80x8C8PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFF0x8CC0x8CCPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFF0x8D00x8D0PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFF0x8D40x8D4PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFF0x8D80x8D8PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFF0x8DC0x8DF0x8E00x8E0PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFF0x8E40x8E4PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFF0x8E80x8E8PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFF0x8EC0x8EF0x8F00x8F0PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFF0x8F40x8F4PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFF0x8F80x8F8PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFF0x8FC0x8FCPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFF0x9000x93F0x9400x940PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFF0x9440x944PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFF0x9480x948PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFF0x94C0x94CPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFF0x9500xB2F0xB300xB30PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFF0xB340xB3F0xB400xB40PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFF0xB440xB44PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFF0xB480xB48PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFF0xB4C0xB7F0xB800xB80PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFF0xB840xB84PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFF0xB880xB8F0xB900xB90PE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFF0xB940xCFFgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDRPF0_TYPE0_HDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr14080x0R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDRPF PCI-Compatible Configuration Space Header Type0registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_IDregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR0_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR1_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR3_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR4_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR5_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REGDEVICE_ID_VENDOR_ID_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr660x0R0xeb011e0aPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REGDevice ID and Vendor ID Register.falsefalsefalsefalsePCI_TYPE0_VENDOR_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr49Vendor ID.The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh, which is an invalid value for Vendor ID.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x1e0aRPCI_TYPE0_DEVICE_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr65Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31160xeb01RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REGSTATUS_COMMAND_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr4020x4R/W0x00100000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_STATUS_COMMAND_REGStatus and Command Register.falsefalsefalsefalsePCI_TYPE0_IO_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr88IO Space Enable.Controls a Function's response to I/O Space accesses. - When this bit is set, the Function is enabled to decode the address and further process I/O Space accesses. - When this bit is clear, all received I/O accesses are caused to be handled as Unsupported Requests.For a Function that does not support I/O Space accesses, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: !has_io_bar ? RO : RW - Dbi: !has_io_bar ? RO : RW 000x0R/WPCI_TYPE0_MEM_SPACE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr107Memory Space Enable.Controls a Function's response to Memory Space accesses. - When this bit is set, the Function is enabled to decode the address and further process Memory Space accesses. - When this bit is clear, all received Memory Space accesses are caused to be handled as Unsupported Requests.For a Function does not support Memory Space accesses, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: !has_mem_bar ? RO : RW - Dbi: !has_mem_bar ? RO : RW 110x0R/WPCI_TYPE0_BUS_MASTER_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr130Bus Master Enable.Controls the ability of a Function to issue Memory and I/O Read/Write requests. - When this bit is set, the Function is allowed to issue Memory or I/O Requests. - When this bit is clear, the Function is not allowed to issue any Memory or I/O Requests.Requests other than Memory or I/O Requests are not controlled by this bit.Note: MSI/MSI-X interrupt Messages are in-band memory writes, setting the Bus Master Enable bit to 0b disables MSI/MSI-X interrupt Messages as well.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WPCI_TYPE0_SPECIAL_CYCLE_OPERATIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_SETDWC_pcie_wire_cpcie_usp_4x8.csr141Special Cycle Enable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.330x0RPCI_TYPE_MWI_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr154Memory Write and Invalidate.This bit was originally described in the PCI Local Bus Specification and thePCI-to-PCI Bridge architecture specification. Its functionality does not applyto PCI Express, the controller hardwires this bit to 0b.440x0RPCI_TYPE_VGA_PALETTE_SNOOPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_SETDWC_pcie_wire_cpcie_usp_4x8.csr166VGA Palette Snoop.This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge architecture specification. Its functionality does not apply to PCI Express, the controller hardwires this bit to 0b.550x0RPCI_TYPE0_PARITY_ERR_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr178Parity Error Response.This bit controls the logging of poisoned TLPs in the Master Data Parity Errorbit in the Status register. For more details see the "Error Registers" section of the PCI Express Base Specification.660x0R/WPCI_TYPE_IDSEL_STEPPINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_SETDWC_pcie_wire_cpcie_usp_4x8.csr189IDSEL Stepping/Wait Cycle Control.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.770x0RPCI_TYPE0_SERRENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_SETDWC_pcie_wire_cpcie_usp_4x8.csr205SERR# Enable.When set, this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function.Note: The errors are reported if enabled either through this bit orthrough the PCI Express specific bits in the Device Control register. For moredetails see the "Error Registers" section of the PCI Express Base Specification.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr213Reserved for future use.990x0RPCI_TYPE0_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr235Interrupt Disable.Controls the ability of a Function to generate INTx emulation interrupts. - When set, Functions are prevented from asserting INTx interrupts.Note: - Any INTx emulation interrupts already asserted by the Function must be deasserted when this bit is Set. INTx interrupts use virtual wires that must, if asserted, be deasserted using the appropriate Deassert_INTx message(s) when this bit is set. - Only the INTx virtual wire interrupt(s) associated with the Function(s) for which this bit is set are affected. - For functions that generate INTx interrupts, this bit is required. For functions that do not generate INTx interrupts, this bit is optional.10100x0R/WPCI_TYPE_RESERVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_SETDWC_pcie_wire_cpcie_usp_4x8.csr244Reserved.15110x00R--16160x0rRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_SETDWC_pcie_wire_cpcie_usp_4x8.csr252Reserved for future use.18170x0RINT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr266Emulation interrupt pending.When set, indicates that an INTx emulation interrupt is pending internally in the Function. Setting the Interrupt Disable bit has no effect on the state of this bit. For Functions that do not generate INTx interrupts, the controller hardwires this bit to 0b.1919RCAP_LISTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_SETDWC_pcie_wire_cpcie_usp_4x8.csr278Capabilities List.Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure, the controller hardwires this bit to 1b.20200x1RFAST_66MHZ_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr28966MHz Capable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.21210x0RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr297Reserved for future use.22220x0RFAST_B2B_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr308Fast Back to Back Transaction Capable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.23230x0RMASTER_DPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr324Master Data Parity Error.This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Function receives a Poisoned Completion - Function transmits a Poisoned RequestIf the Parity Error Response bit is 0b, this bit is never set.24240x0R/W1CDEV_SEL_TIMINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_SETDWC_pcie_wire_cpcie_usp_4x8.csr335DEVSEL Timing.This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this field to 00b.26250x0RSIGNALED_TARGET_ABORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr348Signaled Target Abort.This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. The controller hardwires this bit to 0b for Functions that do not signal Completer Abort.27270x0R/W1CRCVD_TARGET_ABORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr361Received Target Abort.This bit is set when a Requester receives a Completion with Completer Abort Completion Status. For Functions that do not make Non-Posted Requests on their own behalf, the controller hardwires this bit to 0b.28280x0R/W1CRCVD_MASTER_ABORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr375Received Master Abort.This bit is set when a Requester receives a Completion with Unsupported Request Completion Status. For Functions that do not make Non-Posted Requests on their own behalf, the controller hardwires this bit to 0b.29290x0R/W1CSIGNALED_SYS_ERRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_SETDWC_pcie_wire_cpcie_usp_4x8.csr389Signaled System Error.This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL message, and the SERR# Enable bit in the Command register is 1b. For Functions that do not send ERR_FATAL or ERR_NONFATAL messages, the controller hardwires this bit to 0b.30300x0R/W1CDETECTED_PARITY_ERRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_SETDWC_pcie_wire_cpcie_usp_4x8.csr401Detected Parity Error.This bit is set by a Function whenever it receives a Poisoned TLP, regardless of the state the Parity Error Response bit in the Command register.31310x0R/W1CregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_IDCLASS_CODE_REVISION_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr4830x8R0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_CLASS_CODE_REVISION_IDClass Code and Revision ID Register.falsefalsefalsefalseREVISION_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr424Revision ID.The value in this register specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.700x01RPROGRAM_INTERFACEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_SETDWC_pcie_wire_cpcie_usp_4x8.csr444Programming Interface.This field identifies a specific register-level programming interface (if any) so that device independent software can interact with the Function.Encodings for interface are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1580x00RSUBCLASS_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr463Sub-Class Code.Specifies a base class sub-class, which identifies more specifically the operation of the Function.Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23160x00RBASE_CLASS_CODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr482Base Class Code.A code that broadly classifies the type of operation the Function performs.Encodings for base class, are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGBIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr5850xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGBIST, Header Type, Latency Timer, and Cache Line Size Register.falsefalsefalsefalseCACHE_LINE_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr503Cache Line Size.The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However, legacy conventional PCI software may not always be able to program this register correctly especially in the case of Hot-Plug devices. This read-write register is implemented for legacy compatibility purposes but has no effect on any PCI Express devicebehavior.700x00R/WLATENCY_MASTER_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SETDWC_pcie_wire_cpcie_usp_4x8.csr516Latency Timer.The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this register to 00h.1580x00RHEADER_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr527Header Layout.This field identifies the layout of the second part of the predefined header.The controller uses 000 0000b encoding.22160x00RMULTI_FUNCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_SETDWC_pcie_wire_cpcie_usp_4x8.csr551Multi-Function Device. - When set, indicates that the Device may contain multiple Functions, but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear, software must not probe for Functions other than Function 0 unless explicitly indicated by another mechanism, such as an ARI or SR-IOV Capability structure.Except where stated otherwise, it is recommended that this bit be set if there are multiple Functions, and clear if there is only one Function.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RBISTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_SETDWC_pcie_wire_cpcie_usp_4x8.csr584BIST.This register is used for control and status of BIST. For Functions that do not support BIST the controller hardwires the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link.Bit descriptions: - [31]: BIST Capable.When Set, this bit indicates that the Function supports BIST. When Clear, the Function does not support BIST. - [30]: Start BIST.If BIST Capable is Set, Set this bit to invoke BIST. The Function resets the bit when BIST is complete. Software is permitted to fail the device if this bit is not Clear (BIST is not complete) 2 seconds after it had been Set. Writing this bit to 0b has no effect. This bit must be hardwired to 0b if BIST Capable is Clear. - [29:28]: Reserved. - [27:24]: Completion Code.This field encodes the status of the most recent test. A value of 0000b means that the Function has passed its test. Non-zero values mean the Function failed. Function-specific failure codes can be encoded in the non-zero values. This field's value is only meaningful when BIST Capable is Set and Start BIST is Clear. This field must be hardwired to 0000b if BIST Capable is clear.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR0_REGBAR0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr6880x10R/W0x00000004PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BAR0_REGBAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR0_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_SETDWC_pcie_wire_cpcie_usp_4x8.csr620BAR0 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR0_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr648BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR0_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr670BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR0_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr687BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR1_REGBAR1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr7850x14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BAR1_REGBAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR1_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_SETDWC_pcie_wire_cpcie_usp_4x8.csr721BAR1 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR1_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr747BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR1_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr767BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR1_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr784BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR2_REGBAR2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr8880x18R/W0x00000004PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BAR2_REGBAR2 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR2_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_SETDWC_pcie_wire_cpcie_usp_4x8.csr820BAR2 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR2_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr848BAR2 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR2_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr870BAR2 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR2_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr887BAR2 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR3_REGBAR3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr9850x1CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BAR3_REGBAR3 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR3_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_SETDWC_pcie_wire_cpcie_usp_4x8.csr921BAR3 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR3_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr947BAR3 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR3_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr967BAR3 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR3_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr984BAR3 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR4_REGBAR4_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr10880x20R/W0x00000004PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BAR4_REGBAR4 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR4_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_SETDWC_pcie_wire_cpcie_usp_4x8.csr1020BAR4 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR4_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr1048BAR4 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR4_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr1070BAR4 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR4_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr1087BAR4 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.BAR5_REGBAR5_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr11850x24R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_BAR5_REGBAR5 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR5_MEM_IOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_SETDWC_pcie_wire_cpcie_usp_4x8.csr1121BAR5 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR5_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr1147BAR5 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR5_PREFETCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr1167BAR5 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR5_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr1184BAR5 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REGCARDBUS_CIS_PTR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr12060x28R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REGCardBus CIS Pointer Register.falsefalsefalsefalseCARDBUS_CIS_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr1205CardBus CIS Pointer.Its functionality does not apply to PCI Express. It must be hardwired to 0000 0000h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGSUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr12500x2CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGSubsystem ID and Subsystem Vendor ID Register.These registers are used to uniquely identify the add-in card or subsystem where the PCI Express component resides. They provide a mechanism for vendors to distinguish their products from one another even though the assemblies may have the same PCI Express component on them (and, therefore, the same Vendor ID and Device ID).falsefalsefalsefalseSUBSYS_VENDOR_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr1234Subsystem Vendor ID.Subsystem Vendor IDs can be obtained from the PCI SIG and are used to identify the vendor of the add-in card or subsystem. Values for the Subsystem ID are vendor-specific.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0000RSUBSYS_DEV_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr1249Subsystem ID.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31160x0000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REGEXP_ROM_BASE_ADDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr13070x30R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REGExpansion ROM BAR Register. This register handles the base address and size information for this expansion ROM.falsefalsefalsefalseROM_BAR_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr1280Expansion ROM Enable.This bit controls whether or not the Function accepts accesses to its expansion ROM. - When this bit is 0b, the Function's expansion ROM address space is disabled. - When the bit is 1b, address decoding is enabled using the parameters in the other part of the Expansion ROM Base Address register.The Memory Space Enable bit in the Command register has precedence over the Expansion ROM Enable bit. A Function must claim accesses to its expansion ROM only if both the Memory Space Enable bit and the Expansion ROM Enable bit are set.Note: The access attributes of this field are as follows: - Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R 000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr1288Reserved for future use.1010x000REXP_ROM_BASE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_SETDWC_pcie_wire_cpcie_usp_4x8.csr1306Expansion ROM Base Address.Upper 21 bits of the Expansion ROM base address.The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires.Note: The access attributes of this field are as follows: - Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R 31110x000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REGPCI_CAP_PTR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr13410x34R0x00000040PE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_PCI_CAP_PTR_REGCapabilities Pointer Register. This register is used to point to a linked list of capabilities implemented by a Function.falsefalsefalsefalseCAP_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr1333Capabilities Pointer. This register points to a valid capability structure. Either this structure is the PCI Express Capability structure, or a subsequent list item points to the PCI Express Capability structure. The bottom two bits are reserved, the controller sets it to 00b. Software must mask these bits off before using this register as a pointer in Configuration Space to the first entry of a linked list of new capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.700x40RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr1340Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGMAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr14070x3CR/W0x000001ffPE0_DWC_pcie_ctl_AXI_Slave_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGMax_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register. The Interrupt Line register communicates interrupt line routing information. The Interrupt Pin register identifies the legacy interrupt Message(s) the Function uses.falsefalsefalsefalseINT_LINEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_SETDWC_pcie_wire_cpcie_usp_4x8.csr1361Interrupt Line.The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin.Values in this register are programmed by system software and are system architecture specific. The Function itself does not use this value; rather the value in this register is used by device drivers and operating systems.700xffR/WINT_PINPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_SETDWC_pcie_wire_cpcie_usp_4x8.csr1398Interrupt Pin.The Interrupt Pin register identifies the legacy interrupt Message(s) the Function uses.The valid values are: - 01h, 02h, 03h, and 04h: Map to legacy interrupt Messages for INTA, INTB, INTC, and INTD respectively. - 00h: Indicates that the Function uses no legacy interrupt Message(s). - 05h through FFh: Reserved.PCI Express defines one legacy interrupt Message for a single Function device and up to four legacy interrupt Messages for a multi-Function device. For a single Function device, only INTA may be used.Any Function on a multi-Function device can use any of the INTx Messages. If a device implements a single legacy interrupt Message, it must be INTA; if it implements two legacy interrupt Messages, they must be INTA and INTB; and so forth.For a multi-Function device, all Functions may use the same INTx Message or each may have its own (up to a maximum of four Functions) or any combination thereof. A single Function can never generate an interrupt request on more than one INTx Message.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x01RRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr1406Reserved for future use.31160x0000RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_PM_CAPPF0_PM_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr17940x40R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PM_CAPPF PCI Power Management Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PM_CAP.CON_STATUS_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGCAP_ID_NXT_PTR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr16000x0R0x03c35001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PM_CAP_CAP_ID_NXT_PTR_REGPower Management Capabilities Register.falsefalsefalsefalsePM_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr1427Capability ID.This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h.700x01RPM_NEXT_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr1444Next Capability Pointer.This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list, this field is set to 00h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x50RPM_SPEC_VERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SETDWC_pcie_wire_cpcie_usp_4x8.csr1461Version.This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0>.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.18160x3RPME_CLKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_SETDWC_pcie_wire_cpcie_usp_4x8.csr1472PME Clock.Does not apply to PCI Express, the controller hardwires it to 0b.Note: This register field is sticky.19190x0R--20200x0rDSIPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_SETDWC_pcie_wire_cpcie_usp_4x8.csr1491Device Specific Initialization.The DSI bit indicates whether special initialization of this function is required.When set, indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized state.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.21210x0RAUX_CURRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_SETDWC_pcie_wire_cpcie_usp_4x8.csr1524Aux_Current.This 3 bit field reports the Vaux auxiliary current requirements for the function.If this function implements the Data Register, the controller hardwires this field to 000b.If PME_Support is 0 xxxxb (PME assertion from D3cold is not supported), the controller hardwires this field to 0000b.For functions where PME_Support is 1 xxxxb (PME assertion from D3cold is supported), and which do not implement the Data field, the following encodings apply: - b111 375mA Vaux Max. Current Required - b110 320mA Vaux Max. Current Required - b101 270mA Vaux Max. Current Required - b100 220mA Vaux Max. Current Required - b011 160mA Vaux Max. Current Required - b010 100mA Vaux Max. Current Required - b001 55mA Vaux Max. Current Required - b000 0 self poweredNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.24220x7RD1_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr1540D1_Support.If this bit is set, this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.25250x1RD2_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr1556D2_Support.If this bit is set, this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26260x0RPME_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr1599PME_Support.This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages.A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. - bit(27) X XXX1b - PME can be generated from D0 - bit(28) X XX1Xb - PME can be generated from D1 - bit(29) X X1XXb - PME can be generated from D2 - bit(30) X 1XXXb - PME can be generated from D3hot - bit(31) 1 XXXXb - PME can be generated from D3coldBit 31 (PME can be asserted from D3cold) represents a special case. Functions that set this bit require some sort of auxiliary power source. Implementation specific mechanisms are recommended to validate that the power source is available before setting this bit.Each bit that corresponds to a supported D-state must be set for PCI-PCI Bridge structures representing Ports on Root Complexes/Switches to indicate that the Bridge will forward PME Messages. Bit 31 must only be set if the Port is still able to forward PME Messages when main power is not available.The read value from this field is the write value && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where D1_SUPPORT and D2_SUPPORT are fields in this register.The reset value PME_SUPPORT_n && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where PME_SUPPORT_n is a configuration parameter.Note: The access attributes of this field are as follows: - Wire: R - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3127RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PM_CAP.CON_STATUS_REGCON_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr17930x4R/W0x00000008PE0_DWC_pcie_ctl_AXI_Slave_PF0_PM_CAP_CON_STATUS_REGPower Management Control and Status Register.This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs.falsefalsefalsefalsePOWER_STATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_SETDWC_pcie_wire_cpcie_usp_4x8.csr1644PowerState.This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below.You can write to this register; however, the read-back value is the actual power state, not the write value. If you attempt to write an unsupported, optional state to this field, the write operation completes normally; however, the data is discarded and no state change occurs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 10R/WfalsetruefalseD00x0D0 power stateD10x1D1 power stateD20x2D2 power stateD3hot0x3D3hot D3hot power stateRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr1652Reserved for future use.220x0RNO_SOFT_RSTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_SETDWC_pcie_wire_cpcie_usp_4x8.csr1678No_Soft_Reset.This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set, this transition preserves internal function state. The function is in D0Active and no additional software intervention is required. - When clear, this transition results in undefined internal function state.Regardless of this bit, functions that transition from D3hot to D0 by Fundamental Reset will return to D0Uninitialized with only PME context preserved if PME is supported and enabled.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.330x1RRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr1686Reserved for future use.740x0RPME_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr1707PME_En. - When set, the function is permitted to generate a PME. - When clear, the function is not permitted to generate a PME.If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is available this bit is RWS and the bit is not modified by Conventional Reset or FLR.If PME_Support is 0 xxxxb, this field is not sticky (RW).If PME_Support is 0 0000b, the controller hardwires this bit to 0b.Note: This register field is sticky.88R/WDATA_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr1719Data_Select.This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented, this field must be hardwired to 0000b.1290x0RDATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr1733Data_Scale.This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details, see 7.5.2.3 section of PCI Express Base Specification.14130x0RPME_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr1752PME_Status.This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit.If PME_Support bit 31 of the Power Management Capabilities register is clear, this bit is permitted to be hardwired to 0b.Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this register value is not modified by Conventional Reset or FLR.15150x0R/W1CRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr1760Reserved for future use.21160x00RB2_B3_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr1770B2B3 Support for D3hot.For a description of this standard PCIe register field, see the PCI Express Base Specification.22220x0RBUS_PWR_CLK_CON_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr1780Bus Power/Clock Control Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.23230x0RDATA_REG_ADD_INFOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_SETDWC_pcie_wire_cpcie_usp_4x8.csr1792Data.This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field.31240x00RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAPPF0_MSI_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr21920x50R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAPPF MSI Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGPCI_MSI_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr19730x0R/W0x038a7005PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REGMSI Capability Header and Message Control Register.falsefalsefalsefalsePCI_MSI_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr1812Capability ID.Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure.700x05RPCI_MSI_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr1829Next Capability Pointer.This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x70RPCI_MSI_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr1846MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear, the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit to enable MSI. A device driver is prohibited from writing this bit to mask a function's service request. For more details on control of INTx interrupts, see section 7.5.1.1 of PCI Express Base Specification. - If clear, the function is prohibited from using MSI to request service.16160x0R/WPCI_MSI_MULTIPLE_MSG_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr1872Multiple Message Capable.System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors, it requests four by initializing this field to 010b). The encoding is defined as: - 000b: 1 vector requested - 001b: 2 vectors requested - 010b: 4 vectors requested - 011b: 8 vectors requested - 100b: 16 vectors requested - 101b: 32 vectors requested - 110b: Reserved - 111b: ReservedNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.19170x5RPCI_MSI_MULTIPLE_MSG_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr1897Multiple Message Enable.Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a function requests four vectors (indicated by a Multiple Message Capable encoding of 010b), system software can allocate either four, two, or one vector by writing a 010b, 001b, or 000b to this field, respectively. When MSI is enabled, a function will be allocated at least 1 vector. The encoding is defined as: - 000b: 1 vector allocated - 001b: 2 vectors allocated - 010b: 4 vectors allocated - 011b: 8 vectors allocated - 100b: 16 vectors allocated - 101b: 32 vectors allocated - 110b: Reserved - 111b: Reserved22200x0R/WPCI_MSI_64_BIT_ADDR_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr191764 bit address capable. - If set, the function is capable of sending a 64-bit message address. - If clear, the function is not capable of sending a 64-bit message address.This bit must be set if the function is a PCI Express Endpoint.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.23230x1RPCI_PVM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr1930Per-Vector Masking Capable. - If set, the function supports MSI Per-Vector Masking. - If clear, the function does not support MSI Per-Vector Masking.This bit must be set if the function is a PF or VF within an SR-IOV Device.24240x1RPCI_MSI_EXT_DATA_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr1947Extended Message Data Capable. - If set, the function is capable of providing Extended Message Data. - If clear, the function does not support providing Extended Message Data.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.25250x1RPCI_MSI_EXT_DATA_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr1964Extended Message Data Enable. - If set, the function is enabled to provide Extended Message Data. - If clear, the function is not enabled to provide Extended Message Data.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO - Dbi: PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO 26260x0R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr1972Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGMSI_CAP_OFF_04H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr20010x4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_04H_REGMessage Address Register for MSI (Offset 04h).falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr1984Reserved for future use.100x0RPCI_MSI_CAP_OFF_04HPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SETDWC_pcie_wire_cpcie_usp_4x8.csr2000Message Address - System-specified message address.If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set, the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI transaction. Address[1:0] are set to 00b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3120x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGMSI_CAP_OFF_08H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr20810x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_08H_REGFor a function that supports a 32-bit message address, - bits[31:16] of this register represent the Extended Message Data, and - bits[15:0] of this register represent the Message DataFor a function that supports a 64-bit message address (bit 23 in PCI_MSI_CAP_ID_NEXT_CTRL_REG register set), this register represents the Message Upper Address Register for MSI (Offset 08h). It specifies the Message Upper Address (System-specified message upper address). This register is required for PCI Express Endpoints and is optional for other function types. If the Message Enable bit (bit 0 of the Message Control register) is set, the contents of this register (if non-zero) specify the upper 32-bits of a 64-bit message address (Address[63:32]). If the contents of this register are zero, the Function uses the 32 bit address specified by the Message Address register.falsefalsefalsefalsePCI_MSI_CAP_OFF_08HPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SETDWC_pcie_wire_cpcie_usp_4x8.csr2051For a function that supports a 32-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.For a function that supports a 64-bit message address, it contains lower 16 bits of the Message Upper Address.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R 1500x0000R/WPCI_MSI_CAP_OFF_0AHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SETDWC_pcie_wire_cpcie_usp_4x8.csr2080For a function that supports a 32-bit message address, this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is outside the MSI Capability structure and undefined. For the MSI Capability structures with Per-vector Masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is RsvdP. If the Extended Message Data Enable bit (bit 26 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the DWORD Memory Write transaction uses Extended Message Data for the upper 16 bits; otherwise, it uses 0000h for the upper 16 bits.For a function that supports a 64-bit message address, it contains upper 16 bits of the Message Upper Address.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R 31160x0000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGMSI_CAP_OFF_0CH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr21460xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REGFor a function that supports a 32-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message address, this register contains Message Data.falsefalsefalsefalsePCI_MSI_CAP_OFF_0CHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SETDWC_pcie_wire_cpcie_usp_4x8.csr2124For a function that supports a 32-bit message address, this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R 1500x0000R/WPCI_MSI_CAP_OFF_0EHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SETDWC_pcie_wire_cpcie_usp_4x8.csr2145For a function that supports a 32-bit message address, this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data).Note: The access attributes of this field are as follows: - Wire: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO - Dbi: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO 31160x0000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGMSI_CAP_OFF_10H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr21750x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_10H_REGFor a function that supports a 32-bit message address, this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.falsefalsefalsefalsePCI_MSI_CAP_OFF_10HPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SETDWC_pcie_wire_cpcie_usp_4x8.csr2174Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit, contains Mask Bits.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R 3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGMSI_CAP_OFF_14H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr21910x14R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_14H_REGPending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.falsefalsefalsefalsePCI_MSI_CAP_OFF_14HPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SETDWC_pcie_wire_cpcie_usp_4x8.csr2190Pending Bits. For each pending bit that is set, the function has a pending associated message.3100x00000000RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAPPF0_PCIE_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr49670x70R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAPPF PCI Express Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr23490x0R0x0002b010PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPCI Express Capabilities, ID, Next Pointer Register.falsefalsefalsefalsePCIE_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr2210Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure.700x10RPCIE_CAP_NEXT_PTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SETDWC_pcie_wire_cpcie_usp_4x8.csr2225Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580xb0RPCIE_CAP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SETDWC_pcie_wire_cpcie_usp_4x8.csr2249Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number.A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example, through a new Capability field) is permitted to increment this field. All such changes to the PCI Express Capability structure must be software-compatible. Software must check for Capability Version numbers that are greater than or equal to the highest number defined when the software is written, as functions reporting any such Capability Version numbers will contain a PCI Express Capability structure that is compatible with that piece of software.The controller hardwires this field to 2h for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0.Note: This register field is sticky.19160x2RPCIE_DEV_PORT_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr2276Device/Port Type. Indicates the specific type of this PCI Express function.Note: Different functions in a Multi-Function Device can generally be of different types.Defined encodings for functions that implement a Type 00h PCI Configuration Space header are: - 0000b PCI Express Endpoint - 0001b Legacy PCI Express EndpointDefined encodings for functions that implement a Type 01h PCI Configuration Space header are: - 0100b Root Port of PCI Express Root Complex - 0101b Upstream Port of PCI Express Switch - 0110b Downstream Port of PCI Express SwitchAll other encodings are Reserved.Note: Different Endpoint types have notably different requirements in Section 1.3.2 of PCI Express Base Specification regarding I/O resources, Extended Configuration Space, and other capabilities.2320RPCIE_SLOT_IMPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SETDWC_pcie_wire_cpcie_usp_4x8.csr2292Slot Implemented. When set, this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit is undefined for Upstream Ports.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 24240x0RPCIE_INT_MSG_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SETDWC_pcie_wire_cpcie_usp_4x8.csr2334PCIE Interrupt Message Number.For a description of this standard PCIe register field, see the PCI Express Base Specification.Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message generated in association with any of the status bits of this Capability structure.For MSI, the value in this field indicates the offset between the base Message Data and the interrupt message that is generated. Hardware is required to update this field so that it is correct if the number of MSI Messages assigned to the Function changes when software writes to the Multiple Message Enable field in the MSI Message Control register.For MSI-X, the value in this field indicates which MSI-X Table entry is used to generate the interrupt message. The entry must be one of the first 32 entries even if the Function implements more than 32 entries. For a given MSI-X implementation, the entry must remain constant.If both MSI and MSI-X are implemented, they are permitted to use different vectors, though software is permitted to enable only one mechanism at a time. If MSI-X is enabled, the value in this field must indicate the vector for MSI-X. If MSI is enabled or neither is enabled, the value in this field must indicate the vector for MSI. If software enables both MSI and MSI-X at the same time, the value in this field is undefined.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.29250x00RRSVDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SETDWC_pcie_wire_cpcie_usp_4x8.csr2341Reserved.30300x0RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr2348Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGDEVICE_CAPABILITIES_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr26390x4R0x00008fe1PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REGDevice Capabilities Register.The Device Capabilities register identifies PCI Express device function specific capabilities.falsefalsefalsefalsePCIE_CAP_MAX_PAYLOAD_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr2381Max_Payload_Size Supported.This field indicates the maximum payload size that the function can support for TLPs.Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max payload size - 011b: 1024 bytes max payload size - 100b: 2048 bytes max payload size - 101b: 4096 bytes max payload size - 110b: Reserved - 111b: ReservedThe functions of a Multi-Function Device are permitted to report different values for this field.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x1RPCIE_CAP_PHANTOM_FUNC_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr2435Phantom Functions Supported.This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom Functions) with the Tag identifier (see Section 2.2.6.2 of PCI Express Base Specification for a description of Tag Extensions).With every Function in an ARI Device, the Phantom Functions Supported field must be set to 00b. The remainder of this field description applies only to non-ARI Multi-Function Devices.This field indicates the number of most significant bits of the Function Number portion of Requester ID that are logically combined with the Tag identifier.Defined encodings are: - 00b: No Function Number bits are used for Phantom Functions. Multi-Function Devices are permitted to implement up to 8 independent functions. - 01b: The most significant bit of the Function number in Requester ID is used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-3. Functions 0, 1, 2, and 3 are permitted to use Function Numbers 4, 5, 6, and 7 respectively as Phantom Functions. - 10b: The two most significant bits of Function Number in Requester ID are used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-1. Function 0 is permitted to use Function Numbers 2, 4, and 6 for Phantom Functions. Function 1 is permitted to use Function Numbers 3, 5, and 7 as Phantom Functions. - 11b: All 3 bits of Function Number in Requester ID used for Phantom Functions. The device must have a single Function 0 that is permitted to use all other Function Numbers as Phantom Functions.Note: Phantom Function support for the function must be enabled by the Phantom Functions Enable field in the Device Control register before the Function is permitted to use the Function Number field in the Requester ID for Phantom Functions.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.430x0RPCIE_CAP_EXT_TAG_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SETDWC_pcie_wire_cpcie_usp_4x8.csr2462Extended Tag Field Supported.This bit, in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register, indicates the maximum supported size of the Tag field as a Requester. This bit must be set if the 10-Bit Tag Requester Supported bit is set.Defined encodings are: - 0b: 5-bit Tag field supported - 1b: 8-bit Tag field supportedNote: 8-bit Tag field generation must be enabled by the Extended Tag Field Enable bit in the Device Control register of the Requester Function before 8-bit Tags can be generated by the Requester. See Section 2.2.6.2 of PCI Express Base Specificationfor interactions with enabling the use of 10-Bit Tags.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.550x1RPCIE_CAP_EP_L0S_ACCPT_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_SETDWC_pcie_wire_cpcie_usp_4x8.csr2497Endpoint L0s Acceptable Latency. This field indicates the acceptable total latency that an Endpoint can withstand due to the transition from L0s state to the L0 state. It is essentially an indirect measure of the Endpoint’s internal buffering.Power management software uses the reported L0s Acceptable Latency number to compare against the L0s exit latencies reported by all components comprising the data path from this Endpoint to the Root Complex Root Port to determine whether ASPM L0s entry can be used with no loss of performance.Defined encodings are: - 000b: Maximum of 64 ns - 001b: Maximum of 128 ns - 010b: Maximum of 256 ns - 011b: Maximum of 512 ns - 100b: Maximum of 1 us - 101b: Maximum of 2 us - 110b: Maximum of 4 us - 111b: No limitFor functions other than Endpoints, this field is Reserved and the controller hardwires it to 000b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.860x7RPCIE_CAP_EP_L1_ACCPT_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_SETDWC_pcie_wire_cpcie_usp_4x8.csr2532Endpoint L1 Acceptable Latency. This field indicates the acceptable latency that an Endpoint can withstand due to the transition from L1 state to the L0 state. It is essentially an indirect measure of the Endpoint’s internal buffering.Power management software uses the reported L1 Acceptable Latency number to compare against the L1 Exit Latencies reported (see below) by all components comprising the data path from this Endpoint to the Root Complex Root Port to determine whether ASPM L1 entry can be used with no loss of performance.Defined encodings are: - 000b: Maximum of 1 us - 001b Maximum of 2 us - 010b Maximum of 4 us - 011b Maximum of 8 us - 100b Maximum of 16 us - 101b Maximum of 32 us - 110b Maximum of 64 us - 111b No limitFor functions other than Endpoints, this field is Reserved and the controller hardwires it to 000b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W (Sticky) else R(Sticky) Note: This register field is sticky.1190x7RRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr2539Reserved for future use.14120x0RPCIE_CAP_ROLE_BASED_ERR_REPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr2559Role-Based Error Reporting. When set, this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification, Revision 1.0a, and later incorporated into PCI Express Base Specification, Revision 1.1. This bit must be set by all functions conforming to the ECN, PCI Express Base Specification, Revision 1.1., or subsequent PCI Express Base Specification revisions.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.15150x1RRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr2566Reserved for future use.17160x0RPCIE_CAP_CAP_SLOT_PWR_LMT_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr2592Captured Slot Power Limit Value.For a description of this standard PCIe register field, see the PCI Express Base Specification.Captured Slot Power Limit Value (Upstream Ports only). In combination with the Captured Slot Power Limit Scale value, specifies the upper limit on power available to the adapter.Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Captured Slot Power Limit Scale field except when the Captured Slot Power Limit Scale field equals 00b (1.0x) and the Captured Slot Power Limit Value exceeds EFh, then alternative encodings are used (for more details, see section 7.5.3.9 of PCI Express Base Specification).This value is set by the Set_Slot_Power_Limit Message or hardwired to 00h (for more details, see section 6.9 of PCI Express Base Specification).2518RPCIE_CAP_CAP_SLOT_PWR_LMT_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr2612Captured Slot Power Limit Scale.For a description of this standard PCIe register field, see the PCI Express Base Specification.Captured Slot Power Limit Scale (Upstream Ports only). Specifies the scale used for the Slot Power Limit Value.Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001xThis value is set by the Set_Slot_Power_Limit Message or hardwired to 00b (for more details, see section 6.9 of PCI Express Base Specification).2726RPCIE_CAP_FLR_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr2631Function Level Reset Capability. A value of 1b indicates the function supports the optional Function Level Reset mechanism described in section 6.6.2 of of PCI Express Base Specification.This bit applies to Endpoints only. For all other function types the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.28280x0RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr2638Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSDEVICE_CONTROL_DEVICE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr29880x8R/W0x00002010PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUSDevice Control and Device Status Register.This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters.falsefalsefalsefalsePCIE_CAP_CORR_ERR_REPORT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr2662Correctable Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_COR Messages (for more details, see section 6.2.5, section 6.2.6, and section 6.2.10.2 of PCI Express Base Specification). For a Multi-Function device, this bit controls error reporting for each function from point-of-view of the respective function.For a Root Port, the reporting of correctable errors is internal to the root. No external ERR_COR Message is generated.000x0R/WPCIE_CAP_NON_FATAL_ERR_REPORT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr2679Non-Fatal Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_NONFATAL Messages (for more details, see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a Multi-Function Device, this bit controls error reporting for each function from point-of-view of the respective Function.For a Root Port, the reporting of Non-fatal errors is internal to the root. No external ERR_NONFATAL Message is generated.110x0R/WPCIE_CAP_FATAL_ERR_REPORT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr2695Fatal Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_FATAL Messages (for more details, see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function device, this bit controls error reporting for each function from point-of-view of the respective function.For a Root Port, the reporting of Fatal errors is internal to the root. No external ERR_FATAL Message is generated.220x0R/WPCIE_CAP_UNSUPPORT_REQ_REP_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr2709Unsupported Request Reporting Enable.This bit, in conjunction with other bits, controls the signaling of Unsupported Request Errors by sending error Messages (for more details, see section 6.2.5 and section 6.2.6 of PCI Express Base Specification). For a Multi-Function Device, this bit controls error reporting for each Function from point-of-view of the respective Function.330x0R/WPCIE_CAP_EN_REL_ORDERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SETDWC_pcie_wire_cpcie_usp_4x8.csr2729Enable Relaxed Ordering.If this bit is set, the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details, see section 2.2.6.4 and section 2.4 of PCI Express Base Specification).For a function that never sets the Relaxed Ordering attribute in transactions it initiates as a Requester, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x1R/WPCIE_CAP_MAX_PAYLOAD_SIZE_CSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SETDWC_pcie_wire_cpcie_usp_4x8.csr2766Max_Payload_Size.This field sets maximum TLP payload size for the Function. As a Receiver, the Function must handle TLPs as large as the set value. As a Transmitter, the Function must not generate TLPs exceeding the set value. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities (DEVICE_CAPABILITIES_REG) register (for more details, see section 7.5.3.3 of PCI Express Base Specification).Defined encodings for this field are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max payload size - 011b: 1024 bytes max payload size - 100b: 2048 bytes max payload size - 101b: 4096 bytes max payload size - 110b: Reserved - 111b: ReservedFor Functions that support only the 128-byte max payload size, the controller hardwires this field to 000b.System software is not required to program the same value for this field for all the Functions of a Multi-Function device (for more details, see section 2.2.2 of PCI Express Base Specification).For ARI Devices, Max_Payload_Size is determined solely by the setting in Function0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.750x0R/WPCIE_CAP_EXT_TAG_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr2799Extended Tag Field Enable.This bit, in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register, determines how many Tag field bits a Requester is permitted to use.When the 10-Bit Tag Requester Enable bit is clear, - If the Extended Tag Field Enable bit is set, the function is permitted to use an 8-bit Tag field as a Requester - If the Extended Tag Field Enable bit is clear, the Function is restricted to a 5-bit Tag fieldSee section 2.2.6.2 of PCI Express Base Specification for required behavior when the 10-Bit Tag Requester Enable bit is set.If software changes the value of the Extended Tag Field Enable bit while the function has outstanding Non-Posted Requests, the result is undefined.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO 88R/WPCIE_CAP_PHANTOM_FUNC_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr2835Phantom Functions Enable.This bit, in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register, determines how many Tag field bits a Requester is permitted to use.When the 10-Bit Tag Requester Enable bit is clear, - If this bit is set, it enables a function to use unclaimed functions as Phantom functions to extend the number of outstanding transaction identifiers - If this bit is clear, the function is not allowed to use Phantom functionsFor more details, see section 2.2.6.2 of PCI Express Base Specification.Software should not change the value of this bit while the function has outstanding Non-Posted Requests; otherwise, the result is undefined.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO 99RPCIE_CAP_AUX_POWER_PM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr2862Aux Power PM Enable.This bit is derived by sampling the sys_aux_pwr_det input.When set this bit, enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems should continue to indicate PME Aux power requirements. Aux power is allocated as requested in the Aux_Current field of the Power Management Capabilities register (PMC), independent of the PME_En bit in the Power Management Control/Status register (PMCSR). For Multi-Function devices, a component is allowed to draw Aux power if at least one of the functions has this bit set.Note: Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this bit is not modified by Conventional Reset.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: This register field is sticky.1010R/WPCIE_CAP_EN_NO_SNOOPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SETDWC_pcie_wire_cpcie_usp_4x8.csr2889Enable No Snoop.If this bit is set, the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express Base Specification).Note: Setting this bit to 1b should not cause a function to set the No Snoop attribute on all transactions that it initiates. Even when this bit is set, a function is only permitted to set the No Snoop attribute on a transaction when it can guarantee that the address of the transaction is not stored in any cache in the system.The controller hardwires this bit 0b if a function would never set the No Snoop attribute in transactions it initiates.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 11110x0RPCIE_CAP_MAX_READ_REQ_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr2912Max_Read_Request_Size.This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: - 000b: 128 bytes maximum Read Request size - 001b: 256 bytes maximum Read Request size - 010b: 512 bytes maximum Read Request size - 011b: 1024 bytes maximum Read Request size - 100b: 2048 bytes maximum Read Request size - 101b: 4096 bytes maximum Read Request size - 110b: Reserved - 111b: ReservedFor functions that do not generate Read Requests larger than 128 bytes and functions that do not generate Read Requests on their own behalf, the controller implements this field as Read Only (RO) with a value of 000b.14120x2R/W--16150x0rPCIE_CAP_NON_FATAL_ERR_DETECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr2930Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device, each function indicates status of errors as perceived by the respective Function.For functions supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the Uncorrectable Error Mask register.17170x0R/W1C--18180x0rPCIE_CAP_UNSUPPORTED_REQ_DETECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr2945Unsupported Request Detected.This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function Device, each function indicates status of errors as perceived by the respective function.19190x0R/W1CPCIE_CAP_AUX_POWER_DETECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr2958AUX Power Detected.Functions that require Aux power report this bit as set if Aux power is detected by the function.This bit is derived by sampling the sys_aux_pwr_det input.2020RPCIE_CAP_TRANS_PENDINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SETDWC_pcie_wire_cpcie_usp_4x8.csr2979Transactions Pending.Endpoints:When set, this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have completed or have been terminated by the Completion Timeout mechanism. This bit must also be cleared upon the completion of an FLR.Root and Switch Ports:The controller hardwires this bit to 0b.2121RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr2987Reserved for future use.31220x000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGLINK_CAPABILITIES_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr33390xCR0x00400c84PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_LINK_CAPABILITIES_REGLink Capabilities Register.The Link Capabilities register identifies PCI Express Link specific capabilities.falsefalsefalsefalsePCIE_CAP_MAX_LINK_SPEEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SETDWC_pcie_wire_cpcie_usp_4x8.csr3028Max Link Speed.This field indicates the maximum Link speed of the associated Port.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the maximum Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are reserved.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.300x4RPCIE_CAP_MAX_LINK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr3064Maximum Link Width.This field indicates the maximum Link width (xN – corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port), adapter connector (Upstream Port), or in the case of component-to-component connections, the actual wired connection width.Defined encodings are: - 00 0001b x1 - 00 0010b x2 - 00 0100b x4 - 00 1000b x8 - 00 1100b x12 - 01 0000b x16 - 10 0000b x32All other encodings are Reserved.Multi-Function devices associated with an Upstream Port must report the same value in this field for all functions.For a description of this standard PCIe register field, see the PCI Express Base Specification.In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.940x08RPCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr3089Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements, see section 5.4.1 of PCI Express Base Specification.Defined encodings are: - 00b: No ASPM Support - 01b: L0s Supported - 10b: L1 Supported - 11b: L0s and L1 SupportedMulti-Function devices associated with an Upstream Port must report the same value in this field for all functions.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.11100x3RPCIE_CAP_L0S_EXIT_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SETDWC_pcie_wire_cpcie_usp_4x8.csr3147L0s Exit Latency.This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported, the value is undefined; however, see the Implementation Note "Potential Issues With Legacy Software When L0s is Not Supported" in section 5.4.1.1 of PCI Express Base Specification for the recommended value.Defined encodings are: - 000b: Less than 64 ns - 001b: 64 ns to less than 128 ns - 010b: 128 ns to less than 256 ns - 011b: 256 ns to less than 512 ns - 100b: 512 ns to less than 1 us - 101b: 1 us to less than 2 us - 110b: 2 us to 4 us - 111b: More than 4 usNote: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.There are two each of these register fields, this one and a shadow one at the same address.The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request.Common Clock operation is supported (possible) in the controller when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYCommon Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG).The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1412RPCIE_CAP_L1_EXIT_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SETDWC_pcie_wire_cpcie_usp_4x8.csr3201L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported, the value is undefined.Defined encodings are: - 000b: Less than 1us - 001b: 1 us to less than 2 us - 010b: 2 us to less than 4 us - 011b: 4 us to less than 8 us - 100b: 8 us to less than 16 us - 101b: 16 us to less than 32 us - 110b: 32 us to 64 us - 111b: More than 64 μsNote: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.There are two each of these register fields, this one and a shadow one at the same address.The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request.Common Clock operation is supported (possible) in the controller when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYCommon Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG).The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1715RPCIE_CAP_CLOCK_POWER_MANPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SETDWC_pcie_wire_cpcie_usp_4x8.csr3239Clock Power Management. For Upstream Ports, a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the "clock request" (CLKREQ#) mechanism when the Link is in the L1 and L2/L3 Ready Link states. A value of 0b indicates the component does not have this capability and that reference clock(s) must not be removed in these Link states.L1 PM Substates defines other semantics for the CLKREQ# signal, which are managed independently of Clock Power Management.This Capability is applicable only in form factors that support "clock request" (CLKREQ#) capability.For a Multi-Function device associated with an Upstream Port, each Function indicates its capability independently. Power Management configuration software must only permit reference clock removal if all functions of the Multi-Function device indicate a 1b in this bit. For ARI Devices, all Functions must indicate the same value in this bit.For Downstream Ports, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr3255Surprise Down Error Reporting Capable. For a Downstream Port, this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition.For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.Note: This register field is sticky.19190x0RPCIE_CAP_DLL_ACTIVE_REP_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr3274Data Link Layer Link Active Reporting Capable. For a Downstream Port, the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. For a hot-plug capable Downstream Port (as indicated by the Hot-Plug Capable bit of the Slot Capabilities register) or a Downstream Port that supports Link speeds greater than 5.0 GT/s, the controller hardwires this bit to 1b.For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.20200x0RPCIE_CAP_LINK_BW_NOT_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr3296Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting Links wider than x1 and/or multiple Link speeds.This field is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability the controller hardwires this bit to 0b.Note: This register field is sticky.21210x0RPCIE_CAP_ASPM_OPT_COMPLIANCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr3315ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b.Software is permitted to use the value of this bit to help determine whether to enable ASPM or whether to run ASPM compliance tests.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 22220x1RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr3322Reserved for future use.23230x0RPCIE_CAP_PORT_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SETDWC_pcie_wire_cpcie_usp_4x8.csr3338Port Number. This field indicates the PCI Express Port number for the given PCI Express Link.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGLINK_CONTROL_LINK_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr38910x10R/W0x10000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REGLink Control and Link Status Register.This register controls and provides information about PCI Express Link specific parameters.falsefalsefalsefalsePCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SETDWC_pcie_wire_cpcie_usp_4x8.csr3389Active State Power Management (ASPM) Control.This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to enable ASPM.Defined encodings are: - 00b: Disabled - 01b: L0s Entry Enabled - 10b: L1 Entry Enabled - 11b: L0s and L1 Entry EnabledNote: "L0s Entry Enabled" enables the Transmitter to enter L0s. If L0s is supported, the Receiver must be capable of entering L0s even when the Transmitter is disabled from entering L0s (00b or 10b).ASPM L1 must be enabled by software in the Upstream component on a Link prior to enabling ASPM L1 in the Downstream component on that Link. When disabling ASPM L1, software must disable ASPM L1 in the Downstream component on a Link prior to disabling ASPM L1 in the Upstream component on that Link. ASPM L1 must only be enabled on the Downstream component if both components on a Link support ASPM L1.For Multi-Function Devices (including ARI Devices), it is recommended that software program the same value for this field in all Functions. For non-ARI Multi-Function Devices, only capabilities enabled in all Functions are enabled for the component as a whole.For ARI Devices, ASPM Control is determined solely by the setting in Function0, regardless of Function 0's D-state. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.Software must not enable L0s in either direction on a given Link unless components on both sides of the Link each support L0s; otherwise, the result is undefined.100x0R/WRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr3397Reserved for future use.220x0RPCIE_CAP_RCBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SETDWC_pcie_wire_cpcie_usp_4x8.csr3437Read Completion Boundary (RCB).Root Ports:Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB.Defined encodings are: - 0b: 64 byte - 1b: 128 byteThe controller hardwires this bit for a Root Port and returns its RCB support capabilities.Endpoints and Bridges:Optionally set by configuration software to indicate the RCB value of the Root Port Upstream from the Endpoint or Bridge. Refer to Section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB.Defined encodings are: - 0b 64 byte - 1b 128 byteConfiguration software must only set this bit if the Root Port Upstream from the Endpoint or Bridge reports an RCB value of 128 bytes (a value of 1b in the Read Completion Boundary bit).For functions that do not implement this feature, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WPCIE_CAP_LINK_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr3467Link Disable.This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.Writes to this bit are immediately reflected in the value read from the bit, regardless of actual Link state.After clearing this bit, software must honor timing requirements defined in Section 6.6.1 with respect to the first Configuration Read following a Conventional Reset.In a DSP that supports crosslink, the controller gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF.Note: The access attributes of this field are as follows: - Wire: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1 ? RW : RO - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO 44R/WPCIE_CAP_RETRAIN_LINKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SETDWC_pcie_wire_cpcie_usp_4x8.csr3498Retrain Link.A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration, re-entering Recovery is permitted but not required. If the Port is in DPC when a write of 1b to this bit occurs, the result is undefined. Reads of this bit always return 0b.It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. If the LTSSM is not already in Recovery or Configuration, the resulting Link training must use the modified values. If the LTSSM is already in Recovery or Configuration, the modified values are not required to affect the Link training that's already in progress.This bit is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.This bit always returns 0b when read.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description 55R/WPCIE_CAP_COMMON_CLK_CONFIGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SETDWC_pcie_wire_cpcie_usp_4x8.csr3533Common Clock Configuration. When set, this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock.A value of 0b indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock.For non-ARI Multi-Function Devices, software must program the same value for this bit in all Functions. If not all Functions are Set, then the component must as a whole assume that its reference clock is not common with the Upstream component.For ARI Devices, Common Clock Configuration is determined solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.Components utilize this common clock configuration information to report the correct L0s and L1 Exit Latencies.After changing the value in this bit in both components on a Link, software must trigger the Link to retrain by writing a 1b to the Retrain Link bit of the Downstream Port.660x0R/WPCIE_CAP_EXTENDED_SYNCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr3552Extended Synch. When set, this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI Express Base Specification). This mode provides external devices (for example, logic analyzers) monitoring the Link time to achieve bit and Symbol lock before the Link enters the L0 state and resumes communication.For Multi-Function devices if any function has this bit set, then the component must transmit the additional Ordered Sets when exiting L0s or when in Recovery.770x0R/WPCIE_CAP_EN_CLK_POWER_MANPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SETDWC_pcie_wire_cpcie_usp_4x8.csr3597Enable Clock Power Management.Applicable only for Upstream Ports and with form factors that support a "Clock Request" (CLKREQ#) mechanism, this bit operates as follows: - 0b: Clock power management is disabled and device must hold CLKREQ# signal low. - 1b: When this bit is set, the device is permitted to use CLKREQ# signal to power manage Link clock according to protocol defined in appropriate form factor specification.For a non-ARI Multi-Function Device, power-management-configuration software must only Set this bit if all Functions of the Multi-Function Device indicate a 1b in the Clock Power Management bit of the Link Capabilities register. The component is permitted to use the CLKREQ# signal to power manage Link clock only if this bit is Set for all Functions.For ARI Devices, Clock Power Management is enabled solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.The CLKREQ# signal may also be controlled via the L1 PM Substates mechanism. Such control is not affected by the setting of this bit.For Downstream Ports and components that do not support Clock Power Management (as indicated by a 0b value in the Clock Power Management bit of the Link Capabilities register), the controller hardwires this bit to 0b.The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG.Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS Note: This register field is sticky.88R/WPCIE_CAP_HW_AUTO_WIDTH_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr3620Hardware Autonomous Width Disable.When set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RW, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.For components that do not implement the ability autonomously to change Link width, the ciontroller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WPCIE_CAP_LINK_BW_MAN_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr3645Link Bandwidth Management Interrupt Enable. When set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO 1010R/WPCIE_CAP_LINK_AUTO_BW_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr3670Link Autonomous Bandwidth Management Interrupt Enable.When set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO 1111R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr3678Reserved for future use.13120x0RPCIE_CAP_DRS_SIGNALING_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SETDWC_pcie_wire_cpcie_usp_4x8.csr3713DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b: DRS not ReportedIf DRS Supported is set, receiving a DRS Message will set DRS Message Received in the Link Status 2 Register but will otherwise have no effect - 01b: DRS Interrupt EnabledIf the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, and either MSI or MSI-X is enabled, an MSI or MSI-X interrupt is generated using the vector in Interrupt Message Number (section 7.5.3.2) - 10b: DRS to FRS Signaling EnabledIf the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, the Port must send an FRS Message Upstream with the FRS Reason field set to DRS Message Received.Behavior is undefined if this field is set to 10b and the FRS Supported bit in the Device Capabilities 2 Register is Clear.Behavior is undefined if this field is set to 11b.For Downstream Ports with the DRS Supported bit clear in the Link Capabilities 2 register, the controller hardwires this field to 00b.This field is Reserved for Upstream Ports.15140x0RPCIE_CAP_LINK_SPEEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SETDWC_pcie_wire_cpcie_usp_4x8.csr3738Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the current Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are Reserved.The value in this field is undefined when the Link is not up.1916RPCIE_CAP_NEGO_LINK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr3758Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link.Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32All other encodings are Reserved. The value in this field is undefined when the Link is not up.2520RRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_SETDWC_pcie_wire_cpcie_usp_4x8.csr3766Reserved for future use.26260x0RPCIE_CAP_LINK_TRAININGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SETDWC_pcie_wire_cpcie_usp_4x8.csr3787Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery state.This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches, and the controller hardwires it to 0b.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R 2727RPCIE_CAP_SLOT_CLK_CONFIGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SETDWC_pcie_wire_cpcie_usp_4x8.csr3807Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a reference clock on the connector, this bit must be clear.For a Multi-Function Device, each Function must report the same value for this bit.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 28280x1RPCIE_CAP_DLL_ACTIVEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SETDWC_pcie_wire_cpcie_usp_4x8.csr3822Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise.This bit must be implemented if the Data Link Layer Link Active Reporting Capable bit is 1b. Otherwise, the controller hardwires it to 0b.29290x0RPCIE_CAP_LINK_BW_MAN_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr3859Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of 1b to the Retrain Link bit.Note: This bit is set following any write of 1b to the Retrain Link bit, including when the Link is in the process of retraining for some other reason. - Hardware has changed Link speed or width to attempt to correct unreliable Link operation, either through an LTSSM timeout or a higher level process.This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was not indicated as an autonomous change.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.The default value of this bit is 0b.The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R 30300x0RPCIE_CAP_LINK_AUTO_BW_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr3890Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation.This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was indicated as an autonomous change.The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R 31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGDEVICE_CAPABILITIES2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr41490x24R0x8001181fPE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REGDevice Capabilities 2 Register.falsefalsefalsefalsePCIE_CAP_CPL_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SETDWC_pcie_wire_cpcie_usp_4x8.csr3930Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value.This field is applicable only to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is Reserved and must be hardwired to 0000b.Four time value ranges are defined: - Range A: 50 us to 10 ms - Range B: 10 ms to 250 ms - Range C: 250 ms to 4 s - Range D: 4 s to 64 sBits are set according to the list below to show timeout value ranges supported. - 0000b Completion Timeout programming not supported – the Function must implement a timeout value in the range 50 μs to 50 ms. - 0001b Range A - 0010b Range B - 0011b Ranges A and B - 0110b Ranges B and C - 0111b Ranges A, B, and C - 1110b Ranges B, C, and D - 1111b Ranges A, B, C, and DAll other values are Reserved.It is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.300xfRPCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr3948Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism.The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own behalf and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express.This mechanism is optional for Root Ports.For all other Functions this field is Reserved and the controller hardwires this bit to 0b.440x1RPCIE_CAP_ARI_FORWARD_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr3960ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability. For more details, see section 6.13 of PCI Express Base Specification.550x0RPCIE_CAP_ATOMIC_ROUTING_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SETDWC_pcie_wire_cpcie_usp_4x8.csr3972AtomicOp Routing Supported. Applicable only to Switch Upstream Ports, Switch Downstream Ports, and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For more details, see section 6.15 of PCI Express Base Specification.660x0RPCIE_CAP_32_ATOMIC_CPL_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SETDWC_pcie_wire_cpcie_usp_4x8.csr398532-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability. For more details on additional RC requirements, see section 6.15.3.1 of PCI Express Base Specification.770x0RPCIE_CAP_64_ATOMIC_CPL_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SETDWC_pcie_wire_cpcie_usp_4x8.csr399864-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability. For more details on additional RC requirements, see section 6.15.3.1 of PCI Express Base Specification.880x0RPCIE_CAP_128_CAS_CPL_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SETDWC_pcie_wire_cpcie_usp_4x8.csr4009128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details, see section 6.15 of PCI Express Base Specification.990x0RPCIE_CAP_NO_RO_EN_PR2PR_PARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SETDWC_pcie_wire_cpcie_usp_4x8.csr4027No RO-enabled PR-PR Passing. If this bit is set, the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute field being Set.This bit applies only for Switches and RCs that support peer-to-peer traffic between Root Ports. This bit applies only to Posted Requests being forwarded through the Switch or RC and does not apply to traffic originating or terminating within the Switch or RC itself. All Ports on a Switch or RC must report the same value for this bit.For all other functions, this bit must be 0b.10100x0RPCIE_CAP_LTR_SUPPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SETDWC_pcie_wire_cpcie_usp_4x8.csr4050LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism.Root Ports, Switches and Endpoints are permitted to implement this capability.For a Multi-Function Device associated with an Upstream Port, each Function must report the same value for this bit.For Bridges and other Functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(Sticky) else R(Sticky) Note: This register field is sticky.11110x1RPCIE_CAP_TPH_CMPLT_SUPPORT_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr4069TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions, this field is Reserved.Defined Encodings are: - 00b: TPH and Extended TPH Completer not supported. - 01b: TPH Completer supported; Extended TPH Completer not supported. - 10b: Reserved. - 11b: Both TPH and Extended TPH Completer supported.For more details, see section 6.17 of PCI Express Base Specification.12120x1RPCIE_CAP_TPH_CMPLT_SUPPORT_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr4076TPH Completer Supported Bit 1.13130x0RPCIE_CAP2_LN_SYS_CLSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_SETDWC_pcie_wire_cpcie_usp_4x8.csr4093LN System CLS. Applicable only to Root Ports and RCRBs; must be 00b for all other Function types. This field indicates if the Root Port or RCRB supports LN protocol as an LN Completer, and if so, what cacheline size is in effect.Encodings are: - 00b LN Completer either not supported or not in effect - 01b LN Completer with 64-byte cachelines in effect - 10b LN Completer with 128-byte cachelines in effect - 11b ReservedNote: This register field is sticky.15140x0RPCIE_CAP2_10_BIT_TAG_COMP_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr410310-Bit Tag Completer Supported. If this bit is set, the Function supports 10-Bit Tag Completer capability; otherwise, the Function does not. For more details, see section 2.2.6.2. of PCI Express Base Specification.16160x1RPCIE_CAP2_10_BIT_TAG_REQ_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr412110-Bit Tag Requester Supported. If this bit is set, the Function supports 10-Bit Tag Requester capability; otherwise, the Function does not.This bit must not be set if the 10-Bit Tag Completer Supported bit is clear.Note: 10-Bit Tag field generation must be enabled by the 10-Bit Tag Requester Enable bit in the Device Control 2 register of the Requester Function before 10-Bit Tags can be generated by the Requester. For more details, see section 2.2.6.2. of PCI Express Base Specification.17170x0R--23180x0rRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr4128Reserved for future use.30240x00RPCIE_CAP_FRS_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr4148FRS Supported. When set, indicates support for the optional Function Readiness Status (FRS) capability.Must be set for all Functions that support generation or reception capabilities of FRS Messages.Must not be set by Switch Functions that do not generate FRS Messages on their own behalf.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 31310x1RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGDEVICE_CONTROL2_DEVICE_STATUS2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr42790x28R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REGDevice Control 2 and Status 2 Register.falsefalsefalsefalsePCIE_CAP_CPL_TIMEOUT_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr4207Completion Timeout Value. In device Functions that support Completion Timeout programmability, this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is Reserved and controller hardwires it to 0000b.A Function that does not support this optional capability must hardwire this field to 0000b and is required to implement a timeout value in the range 50 μs to 50 ms. Functions that support Completion Timeout programmability must support the values given below corresponding to the programmability ranges indicated in the Completion Timeout Ranges Supported field.Defined encodings: - 0000b Default range: 50 μs to 50 msIt is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.Values available if Range A (50 μs to 10 ms) programmability range is supported: - 0001b: 50 μs to 100 μs - 0010b: 1 ms to 10 msValues available if Range B (10 ms to 250 ms) programmability range is supported: - 0101b 16 ms to 55 ms - 0110b 65 ms to 210 msValues available if Range C (250 ms to 4 s) programmability range is supported: - 1001b 260 ms to 900 ms - 1010b 1 s to 3.5 sValues available if the Range D (4 s to 64 s) programmability range is supported: - 1101b 4 s to 13 s - 1110b 17 s to 64 sValues not defined above are Reserved.Software is permitted to change the value in this field at any time. For Requests already pending when the Completion Timeout Value is changed, hardware is permitted to use either the new or the old value for the outstanding Requests, and is permitted to base the start time for each Request either on when this value was changed or on when each request was issued.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300x0R/WPCIE_CAP_CPL_TIMEOUT_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr4228Completion Timeout Disable. When set, this bit disables the Completion Timeout mechanism.This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this optional capability are permitted to hardwire this bit to 0bSoftware is permitted to set or clear this bit at any time. When set, the Completion Timeout detection mechanism is disabled. If there are outstanding Requests when the bit is cleared, it is permitted but not required for hardware to apply the completion timeout mechanism to the outstanding Requests. If this is done, it is permitted to base the start time for each Request on either the time this bit was cleared or the time each Request was issued.440x0R/WPCIE_CAP_ARI_FORWARD_SUPPORT_CSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SETDWC_pcie_wire_cpcie_usp_4x8.csr4242ARI Forwarding Enable. When set, the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request, permitting access to Extended Functions in an ARI Device immediately below the Port. For more details, see Section 6.13 of PCI Express Base Specification.550x0R--960x0rPCIE_CAP_LTR_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr4278LTR Mechanism Enable. When set to 1b, this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages.For a Multi-Function Device associated with an Upstream Port of a device that implements LTR, the bit in Function 0 is RW, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is RsvdP.Functions that do not implement the LTR mechanism are permitted to hardwire this bit to 0b.For Downstream Ports, this bit must be reset to the default value if the Port goes to DL_Down status.The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG.Note: RW for function #0 and RsdvP for all other functions.Note: The access attributes of this field are as follows: - Wire: if (pf=0 && DEVICE_CAPABILITIES2_REG.PCIE_CAP_LTR_SUPP) then R/W else R - Dbi: if (pf=0 && DEVICE_CAPABILITIES2_REG.PCIE_CAP_LTR_SUPP) then R/W else R 10100x0R/W--31110x0rregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGLINK_CAPABILITIES2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr44400x2CR0x81800000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_LINK_CAPABILITIES2_REGLink Capabilities 2 Register.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr4290Reserved for future use.000x0RPCIE_CAP_SUPPORT_LINK_SPEED_VECTORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr4320Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit, a value of 1b indicates that the corresponding Link speed is supported; otherwise, the Link speed is not supported. For more details, see section 8.2.1 of PCI Express Base Specification.Bit definitions within this field are: - Bit 0 2.5 GT/s - Bit 1 5.0 GT/s - Bit 2 8.0 GT/s - Bit 3 16.0 GT/s - Bit 4 32.0 GT/s - Bits 6:5 RsvdPMulti-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0101) ? 0011111 : (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register.71RPCIE_CAP_CROSS_LINK_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr4348Crosslink Supported. When set to 1b, this bit indicates that the associated Port supports crosslinks (for more details, see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link speeds of 8.0 GT/s or higher, this bit indicates that the associated Port does not support crosslinks. When set to 0b on a Port that only supports Link speeds of 2.5 GT/s or 5.0 GT/s, this bit provides no information regarding the Port’s level of crosslink support.It is recommended that this bit be Set in any Port that supports crosslinks even though doing so is only required for Ports that also support operating at 8.0 GT/s or higher Link speeds.Note: Software should use this bit when referencing fields whose definition depends on whether or not the Port supports crosslinks (for more details, see section 7.7.3.4 of PCI Express Base Specification).Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.880x0RRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr4355Reserved for future use.2290x0000RPCIE_CAP_RETIMER_PRE_DET_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr4380Retimer Presence Detect Supported. When set to 1b, this bit indicates that the associated Port supports detection and reporting of Retimer presence.This bit must be set to 1b in a Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher.It is permitted to be set to 1b regardless of the supported Link speeds.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 23230x1RPCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr4407Two Retimers Presence Detect Supported. When set to 1b, this bit indicates that the associated Port supports detection and reporting of two Retimers presence.This bit must be set to 1b in a Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher.It is permitted to be set to 1b regardless of the supported Link speeds if the Retimer Presence Detect Supported bit is also set to 1b.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 24240x1RRSVDP_25PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_SETDWC_pcie_wire_cpcie_usp_4x8.csr4414Reserved for future use.30250x00RDRS_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr4439DRS Supported. When set, indicates support for the optional Device Readiness Status (DRS) capability.Must be Set in Downstream Ports that support DRS.Must be Set in Downstream Ports that support FRS.For Upstream Ports that support DRS, it is strongly recommended that this bit be Set in Function 0. For all other Functions associated with an Upstream Port, this bit must be Clear.127Must be Clear in Functions that are not associated with a Port.RsvdP in all other Functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31310x1RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGLINK_CONTROL2_LINK_STATUS2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr49660x30R/W0x00010000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REGLink Control 2 and Status 2 Register.falsefalsefalsefalsePCIE_CAP_TARGET_LINK_SPEEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SETDWC_pcie_wire_cpcie_usp_4x8.csr4504Target Link Speed. For Downstream Ports, this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the desired target Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are Reserved.If a value is written to this field that does not correspond to a supported speed (as indicated by the Supported Link Speeds Vector), the result is undefined.If either of the Enter Compliance or Enter Modified Compliance bits are implemented, then this field must also be implemented.The default value of this field is the highest Link speed supported by the component (as reported in the Max Link Speed field of the Link Capabilities register) unless the corresponding platform/form factor requires a different default value.For both Upstream and Downstream Ports, this field is used to set the target compliance mode speed when software is using the Enter Compliance bit to force a Link into compliance mode.For Upstream Ports, if the Enter Compliance bit is Clear, this field is permitted to have no effect.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.Components that support only the 2.5 GT/s speed are permitted to hardwire this field to 0000b.For a description of this standard PCIe register field, see the PCI Express Base Specification. In M-PCIe mode, the contents of this field are derived from other registers.Note: This register field is sticky.30R/WPCIE_CAP_ENTER_COMPLIANCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr4537Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by setting this bit to 1b in both components on a Link and then initiating a hot reset on the Link.Default value of this bit following Fundamental Reset is 0b.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this bit is of type RsvdP.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.Note: This register field is sticky.440x0R/WPCIE_CAP_HW_AUTO_SPEED_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr4562Hardware Autonomous Speed Disable. When set, this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial transition to the highest supported common link speed is not blocked by this bit.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.Functions that do not implement the associated mechanism are permitted to hardwire this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.550x0R/WPCIE_CAP_SEL_DEEMPHASISPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SETDWC_pcie_wire_cpcie_usp_4x8.csr4587Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed, this bit is used to control the transmit de-emphasis of the link in specific situations. For more details, see section 4.2.6 of PCI Express Base Specification.Encodings: - 1b: -3.5 dB - 0b: -6 dBWhen the Link is not operating at 5.0 GT/s speed, the setting of this bit has no effect. Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.Note: This register field is sticky.660x0RPCIE_CAP_TX_MARGINPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SETDWC_pcie_wire_cpcie_usp_4x8.csr4621Transmit Margin – This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base Specification for details of how the Transmitter voltage level is determined in various states).Encodings: - 000b: Normal operating range - 001b-111b: As defined in Section 8.3.4 not all encodings are required to be implemented.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 000b.This field is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.Note: This register field is sticky.970x0R/WPCIE_CAP_ENTER_MODIFIED_COMPLIANCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr4648Enter Modified Compliance. When this bit is set to 1b, the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.10100x0R/WPCIE_CAP_COMPLIANCE_SOSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SETDWC_pcie_wire_cpcie_usp_4x8.csr4675Compliance SOS. When set to 1b, the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this bit is of type RsvdP.This bit is applicable when the Link is operating at 2.5 GT/s or 5.0 GT/s data rates only.For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.11110x0R/WPCIE_CAP_COMPLIANCE_PRESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SETDWC_pcie_wire_cpcie_usp_4x8.csr4717Compliance Preset/De-emphasis.For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in section 4.2.3.2 of PCI Express Base Specification . Results are undefined if a reserved preset encoding is used when entering Polling.Compliance in this way.For 5.0 GT/s Data Rate: This field sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.Defined Encodings are: - 0001b: -3.5 dB - 0000b: -6 dBWhen the Link is operating at 2.5 GT/s, the setting of this field has no effect. Components that support only 2.5 GT/s speed are permitted to hardwire this field to 0000b.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this field is of type RsvdP.This field is intended for debug and compliance testing purposes. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.15120x0R/WPCIE_CAP_CURR_DEEMPHASISPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SETDWC_pcie_wire_cpcie_usp_4x8.csr4743Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed, this bit reflects the level of de-emphasis.Encodings: - 1b: -3.5 dB - 0b: -6 dBThe value in this bit is undefined when the Link is not operating at 5.0 GT/s speed.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.For components that support speeds greater than 2.5 GT/s, Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions of the Port. In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE.16160x1RPCIE_CAP_EQ_CPLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_SETDWC_pcie_wire_cpcie_usp_4x8.csr4765Equalization 8.0 GT/s Complete. When set to 1b, this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.17170x0RPCIE_CAP_EQ_CPL_P1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_SETDWC_pcie_wire_cpcie_usp_4x8.csr4787Equalization 8.0 GT/s Phase 1 Successful. When set to 1b, this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.18180x0RPCIE_CAP_EQ_CPL_P2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_SETDWC_pcie_wire_cpcie_usp_4x8.csr4809Equalization 8.0 GT/s Phase 2 Successful. When set to 1b, this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.19190x0RPCIE_CAP_EQ_CPL_P3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_SETDWC_pcie_wire_cpcie_usp_4x8.csr4831EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b, this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.20200x0RPCIE_CAP_LINK_EQ_REQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr4849Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details, see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.21210x0R/W1CPCIE_CAP_RETIMER_PRE_DETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_SETDWC_pcie_wire_cpcie_usp_4x8.csr4875Retimer Presence Detected. When set to 1b, this bit indicates that a Retimer was present during the most recent Link negotiation. For more details, see section 4.2.6.3.5.1 of PCI Express Base Specification.This bit is required for Ports that have the Retimer Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.For Ports that have the Retimer Presence Detect Supported bit set to 0b, the controller hardwires this bit to 0b.For Multi-Function Devices associated with an Upstream Port, this bit must be implemented in Function 0 and is RsvdZ in all other Functions.Note: This register field is sticky.22220x0RPCIE_CAP_TWO_RETIMERS_PRE_DETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SETDWC_pcie_wire_cpcie_usp_4x8.csr4901Two Retimers Presence Detected. When set to 1b, this bit indicates that two Retimers were present during the most recent Link negotiation. For more details, see section 4.2.6.3.5.1 of PCI Express Base Specification.This bit is required for Ports that have the Two Retimers Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.Ports that have the Two Retimers Presence Detect Supported bit set to 0b are permitted to hardwire this bit to 0b.For Multi-Function Devices associated with an Upstream Port, this bit must be implemented in Function 0 and RsvdZ in all other Functions.Note: This register field is sticky.23230x0R--25240x0rRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_SETDWC_pcie_wire_cpcie_usp_4x8.csr4909Reserved for future use.27260x0RDOWNSTREAM_COMPO_PRESENCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr4949Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component, if any, connected to the Link; defined values are: - 000b: Link Down – Presence Not Determined - 001b: Link Down – Component Not Present indicates the Downstream Port (DP) has determined that a Downstream Component is not present - 010b: Link Down – Component Present indicates the DP has determined that a Downstream Component is present, but the Data Link Layer is not active - 011b: Reserved - 100b: Link Up – Component Presentindicates the DP has determined that a Downstream Component is present, but no DRS Message has been received since the Data Link Layer became active - 101b: Link Up – Component Present and DRS Received indicates the DP has received a DRS Message since the Data Link Layer became active - 110b: Reserved - 111b: ReservedComponent Presence state must be determined by the logical "OR" of the Physical Layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism implemented for the Link. If no out-of-band presence detect mechanism is implemented, then Component Presence state must be determined solely by the Physical Layer in-band presence detect mechanism.This field must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities 2 register.This field is RsvdZ for all other Functions.30280x0RDRS_MESSAGE_RECEIVEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_SETDWC_pcie_wire_cpcie_usp_4x8.csr4965DRS Message Received. This bit must be set whenever the Port receives a DRS Message.This bit must be cleared in DL_Down.This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities 2 register.This bit is RsvdZ for all other Functions.31310x0RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAPPF0_MSIX_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr51690xB0R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAPPF MSI-X Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGPCI_MSIX_CAP_ID_NEXT_CTRL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr50580x0R/W0x00800011PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REGMSI-X Capability ID, Next Pointer, Control Registers.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr4986MSI-X Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x11RPCI_MSIX_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr5002MSI-X Next Capability Pointer.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x00RPCI_MSIX_TABLE_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr5027MSI-X Table Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26160x080RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr5035Reserved for future use.29270x0RPCI_MSIX_FUNCTION_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5048Function Mask.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30300x0R/WPCI_MSIX_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr5057MSI-X Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGMSIX_TABLE_OFFSET_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr51130x4R0x00000004PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REGMSI-X Table Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_BIRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_SETDWC_pcie_wire_cpcie_usp_4x8.csr5088MSI-X Table BAR Indicator Register Field.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table BAR Indicator Register" (PCI_MSIX_BIR field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_BIR field in the PF MSIX_TABLE_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x4RPCI_MSIX_TABLE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr5112MSI-X Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Offset" (PCI_MSIX_TABLE_OFFSET field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_OFFSET field in the PF MSIX_TABLE_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3130x00000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGMSIX_PBA_OFFSET_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr51680x8R0x00008004PE0_DWC_pcie_ctl_AXI_Slave_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REGMSI-X PBA Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_PBA_BIRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_SETDWC_pcie_wire_cpcie_usp_4x8.csr5143MSI-X PBA BIR.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA BIR" (PCI_MSIX_PBA_BIR field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_BIR field in the PF MSIX_PBA_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x4RPCI_MSIX_PBA_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr5167MSI-X PBA Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA Offset" (PCI_MSIX_PBA_OFFSET field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_OFFSET field in the PF MSIX_PBA_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3130x00001000RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAPPF0_AER_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr65900x100R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAPPF Advanced Error Reporting Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFAER_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr52280x0R0x14820001PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_AER_EXT_CAP_HDR_OFFAdvanced Error Reporting Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr5195AER Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0001RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr5211Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x2RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr5227Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x148RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFUNCORR_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr54040x4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_UNCORR_ERR_STATUS_OFFUncorrectable Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr5241Reserved for future use.300x0RDL_PROTOCOL_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5251Data Link Protocol Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.44R/W1CSURPRISE_DOWN_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5261Surprise Down Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.55R/W1CRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr5269Reserved for future use.1160x00RPOIS_TLP_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5280Poisoned TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0R/W1CFC_PROTOCOL_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5290Flow Control Protocol Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.1313R/W1CCMPLT_TIMEOUT_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5301Completion Timeout Status.For a description of this standard PCIe register field, see the PCI Express Specification.14140x0R/W1CCMPLT_ABORT_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5312Completer Abort Status.For a description of this standard PCIe register field, see the PCI Express Specification.15150x0R/W1CUNEXP_CMPLT_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5323Unexpected Completion Status.For a description of this standard PCIe register field, see the PCI Express Specification.16160x0R/W1CREC_OVERFLOW_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5333Receiver Overflow Status.For a description of this standard PCIe register field, see the PCI Express Specification.1717R/W1CMALF_TLP_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5343Malformed TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.1818R/W1CECRC_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5357ECRC Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.Note:If CX_ECRC_ENABLE=0 the register field always reads 0.19190x0R/W1CUNSUPPORTED_REQ_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5368Unsupported Request Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.20200x0R/W1C--21210x0rINTERNAL_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5387Uncorrectable Internal Error Status.For a description of this standard PCIe register field, see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it detects internal uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these errors to drive the app_err_bus[9] input. For more details, see the "Data Integrity (Wire, Datapath, and RAM Protection)" section in the Databook.22220x0R/W1CRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr5395Reserved for future use.23230x0R--26240x0rRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr5403Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFUNCORR_ERR_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr56130x8R/W0x00400000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_UNCORR_ERR_MASK_OFFUncorrectable Error Mask Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr5417Reserved for future use.300x0RDL_PROTOCOL_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5428Data Link Protocol Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.440x0R/WSURPRISE_DOWN_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5440Surprise Down Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x0RRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr5448Reserved for future use.1160x00RPOIS_TLP_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5459Poisoned TLP Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WFC_PROTOCOL_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5470Flow Control Protocol Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x0R/WCMPLT_TIMEOUT_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5481Completion Timeout Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x0R/WCMPLT_ABORT_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5492Completer Abort Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x0R/WUNEXP_CMPLT_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5503Unexpected Completion Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.16160x0R/WREC_OVERFLOW_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5514Receiver Overflow Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.17170x0R/WMALF_TLP_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5525Malformed TLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.18180x0R/WECRC_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5539ECRC Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WUNSUPPORTED_REQ_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5550Unsupported Request Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.20200x0R/WACS_VIOLATION_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5573ACS Violation Mask.Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors.The bit is Read-Only Zero for upstream ports, when ACS P2P Egress Control Enable is not set.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: if (acs_viol_svrity_mask_wr_en == 1) then R/W (Sticky) else R(Sticky) - Dbi: if (acs_viol_svrity_mask_wr_en == 1) then R/W (Sticky) else R(Sticky) Note: This register field is sticky.21210x0RINTERNAL_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5584Uncorrectable Internal Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.22220x1R/WRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr5592Reserved for future use.23230x0RATOMIC_EGRESS_BLOCKED_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5604AtomicOp Egress Block Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.24240x0R--26250x0rRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr5612Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFUNCORR_ERR_SEV_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr58020xCR/W0x00462030PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_UNCORR_ERR_SEV_OFFUncorrectable Error Severity Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr5626Reserved for future use.300x0RDL_PROTOCOL_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr5637Data Link Protocol Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.440x1R/WSURPRISE_DOWN_ERR_SVRITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr5649Surprise Down Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x1RRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr5657Reserved for future use.1160x00RPOIS_TLP_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr5668Poisoned TLP Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WFC_PROTOCOL_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr5679Flow Control Protocol Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x1R/WCMPLT_TIMEOUT_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr5690Completion Timeout Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x0R/WCMPLT_ABORT_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr5701Completer Abort Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x0R/WUNEXP_CMPLT_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr5712Unexpected Completion Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.16160x0R/WREC_OVERFLOW_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr5723Receiver Overflow Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.17170x1R/WMALF_TLP_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr5734Malformed TLP Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.18180x1R/WECRC_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr5748ECRC Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WUNSUPPORTED_REQ_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr5759Unsupported Request Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.20200x0R/W--21210x0rINTERNAL_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr5770Uncorrectable Internal Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.22220x1R/WRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr5778Reserved for future use.23230x0RATOMIC_EGRESS_BLOCKED_ERR_SEVERITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr5793AtomicOp Egress Blocked Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.24240x0R--26250x0rRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr5801Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFCORR_ERR_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr59200x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_CORR_ERR_STATUS_OFFCorrectable Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRX_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5818Receiver Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.000x0R/W1CRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr5826Reserved for future use.510x00RBAD_TLP_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5837Bad TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.660x0R/W1CBAD_DLLP_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5848Bad DLLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.770x0R/W1CREPLAY_NO_ROLEOVER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5859REPLAY_NUM Rollover Status.For a description of this standard PCIe register field, see the PCI Express Specification.880x0R/W1CRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr5867Reserved for future use.1190x0RRPL_TIMER_TIMEOUT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5878Replay Timer Timeout Status.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0R/W1CADVISORY_NON_FATAL_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5889Advisory Non-Fatal Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.13130x0R/W1CCORRECTED_INT_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5900Corrected Internal Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.14140x0R/W1CHEADER_LOG_OVERFLOW_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr5911Header Log Overflow Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.15150x0R/W1CRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr5919Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFCORR_ERR_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr60380x14R/W0x0000e000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_CORR_ERR_MASK_OFFCorrectable Error Mask Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRX_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5936Receiver Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr5944Reserved for future use.510x00RBAD_TLP_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5955Bad TLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.660x0R/WBAD_DLLP_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5966Bad DLLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.770x0R/WREPLAY_NO_ROLEOVER_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5977REPLAY_NUM Rollover Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr5985Reserved for future use.1190x0RRPL_TIMER_TIMEOUT_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr5996Replay Timer Timeout Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WADVISORY_NON_FATAL_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr6007Advisory Non-Fatal Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x1R/WCORRECTED_INT_ERR_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr6018Corrected Internal Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x1R/WHEADER_LOG_OVERFLOW_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr6029Header Log Overflow Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x1R/WRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr6037Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFADV_ERR_CAP_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr61490x18R/W0x000000a0PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFFAdvanced Error Capabilities and Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFIRST_ERR_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr6057First Error Pointer.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.400x00RECRC_GEN_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr6069ECRC Generation Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x1RECRC_GEN_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr6080ECRC Generation Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.660x0R/WECRC_CHECK_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr6092ECRC Check Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.770x1RECRC_CHECK_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr6103ECRC Check Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.880x0R/WMULTIPLE_HEADER_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr6115Multiple Header Recording Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.990x0RMULTIPLE_HEADER_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr6130Multiple Header Recording Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.10100x0R--11110x0rCTO_PRFX_HDR_LOG_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr6140TLP Prefix Log Present.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_SETDWC_pcie_wire_cpcie_usp_4x8.csr6148Reserved for future use.31130x00000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFHDR_LOG_0_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr62080x1CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_HDR_LOG_0_OFFHeader Log Register 0.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFIRST_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6168Byte 0 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RFIRST_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6181Byte 1 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RFIRST_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6194Byte 2 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RFIRST_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6207Byte 3 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFHDR_LOG_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr62670x20R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_HDR_LOG_1_OFFHeader Log Register 1.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseSECOND_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6227Byte 0 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RSECOND_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6240Byte 1 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RSECOND_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6253Byte 2 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RSECOND_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6266Byte 3 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFHDR_LOG_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr63260x24R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_HDR_LOG_2_OFFHeader Log Register 2.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseTHIRD_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6286Byte 0 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RTHIRD_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6299Byte 1 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RTHIRD_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6312Byte 2 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RTHIRD_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6325Byte 3 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFHDR_LOG_3_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr63850x28R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_HDR_LOG_3_OFFHeader Log Register 3.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFOURTH_DWORD_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6345Byte 0 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RFOURTH_DWORD_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6358Byte 1 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RFOURTH_DWORD_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6371Byte 2 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RFOURTH_DWORD_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6384Byte 3 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFTLP_PREFIX_LOG_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr64360x38R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFFTLP Prefix Log Register 1.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_1_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6402Byte 0 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_1_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6413Byte 1 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_1_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6424Byte 2 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_1_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6435Byte 3 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFTLP_PREFIX_LOG_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr64870x3CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFFTLP Prefix Log Register 2.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_2_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6453Byte 0 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_2_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6464Byte 1 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_2_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6475Byte 2 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_2_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6486Byte 3 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFTLP_PREFIX_LOG_3_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr65380x40R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFFTLP Prefix Log Register 3.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_3_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6504Byte 0 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_3_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6515Byte 1 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_3_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6526Byte 2 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_3_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6537Byte 3 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFTLP_PREFIX_LOG_4_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr65890x44R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFFTLP Prefix Log Register 4.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_4_FIRST_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6555Byte 0 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_4_SECOND_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6566Byte 1 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_4_THIRD_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6577Byte 2 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_4_FOURTH_BYTEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6588Byte 3 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAPPF0_VC_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr75820x148R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAPVirtual Channel Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_BASEregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_BASEVC_BASEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr66490x0R0x19810002PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_VC_BASEVC Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PCIE_EXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr6616VC Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0002RVC_CAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr6632Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RVC_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr6648Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x198RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1VC_CAPABILITIES_REG_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr67190x4R0x00000003PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_VC_CAPABILITIES_REG_1Port VC Capability Register 1.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_EXT_VC_CNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr6664Extended VC Count.For a description of this standard PCIe register field, see the PCI Express Base Specification.200x3RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr6671Reserved for future use.330x0RVC_LOW_PRI_EXT_VC_CNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr6686Low Priority Extended VC Count.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.640x0RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr6693Reserved for future use.770x0RVC_REFERENCE_CLOCKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_SETDWC_pcie_wire_cpcie_usp_4x8.csr6702Reference Clock.For a description of this standard PCIe register field, see the PCI Express Base Specification.980x0RVC_PORT_ARBI_TBL_ENTRY_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6711Port Arbitration Table Entry Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.11100x0RRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr6718Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2VC_CAPABILITIES_REG_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr67570x8R0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_VC_CAPABILITIES_REG_2Port VC Capability Register 2.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_ARBI_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr6740VC Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.300x1RRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr6747Reserved for future use.2340x00000RVC_ARBI_TABLE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr6756VC Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGVC_STATUS_CONTROL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr68080xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_VC_STATUS_CONTROL_REGPort VC Control and Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_LOAD_VC_ARBI_TABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr6772Requests Hardware to Load VC Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_ARBI_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr6781VC Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.310x0R/WRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr6789Reserved for future use.1540x000RVC_ARBI_TABLE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr6799VC Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_SETDWC_pcie_wire_cpcie_usp_4x8.csr6807Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0RESOURCE_CAP_REG_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr68730x10R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC0VC Resource Capability Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr6823Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr6830Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr6843Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr6856Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr6863Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr6872Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0RESOURCE_CON_REG_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr69620x14R/W0x800000ffPE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC0VC Resource Control Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr6888Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RVC_TC_MAP_VC0_BIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr6897Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x7fR/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr6905Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr6915Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr6925Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.17170x0RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr6933Reserved for future use.23180x00RVC_ID_VCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_SETDWC_pcie_wire_cpcie_usp_4x8.csr6943VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr6951Reserved for future use.30270x0RVC_ENABLE_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr6961VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x1RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0RESOURCE_STATUS_REG_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr70020x18R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0VC Resource Status Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr6975Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr6984Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr6994VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr7001Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1RESOURCE_CAP_REG_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr70670x1CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC1VC Resource Capability Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7017VC1 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr7024Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7037VC1 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7050VC1 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr7057Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7066VC1 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1RESOURCE_CON_REG_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr71550x20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC1VC Resource Control Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7082VC1 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC1_BIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7091VC1 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr7099Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7109VC1 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7119VC1 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_SETDWC_pcie_wire_cpcie_usp_4x8.csr7127Reserved for future use.23200x0RVC_ID_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7137VC1 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr7145Reserved for future use.30270x0RVC_ENABLE_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7154VC1 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1RESOURCE_STATUS_REG_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr71950x24R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1VC Resource Status Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr7168Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7177VC1 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7187VC1 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr7194Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2RESOURCE_CAP_REG_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr72600x28R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC2VC Resource Capability Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7210VC2 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr7217Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7230VC2 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7243VC2 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr7250Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7259VC2 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2RESOURCE_CON_REG_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr73480x2CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC2VC Resource Control Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7275VC2 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC2_BIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7284VC2 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr7292Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7302VC2 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7312VC2 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_SETDWC_pcie_wire_cpcie_usp_4x8.csr7320Reserved for future use.23200x0RVC_ID_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7330VC2 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr7338Reserved for future use.30270x0RVC_ENABLE_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7347VC2 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2RESOURCE_STATUS_REG_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr73880x30R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2VC Resource Status Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr7361Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7370VC2 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7380VC2 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr7387Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3RESOURCE_CAP_REG_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr74530x34R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC3VC Resource Capability Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7403VC3 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr7410Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7423VC3 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7436VC3 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr7443Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7452VC3 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3RESOURCE_CON_REG_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr75410x38R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC3VC Resource Control Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7468VC3 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC3_BIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7477VC3 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr7485Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7495VC3 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7505VC3 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_SETDWC_pcie_wire_cpcie_usp_4x8.csr7513Reserved for future use.23200x0RVC_ID_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7523VC3 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr7531Reserved for future use.30270x0RVC_ENABLE_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7540VC3 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3RESOURCE_STATUS_REG_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr75810x3CR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3VC Resource Status Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr7554Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7563VC3 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7573VC3 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr7580Reserved for future use.31180x0000RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAPPF0_SPCIE_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr82790x198R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAPSecondary PCI Express Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGSPCIE_CAP_HEADER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr76410x0R0x1b810019PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REGSPCIE Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr7608Secondary PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0019RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr7624Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr7640Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x1b8RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGLINK_CONTROL3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr76820x4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_LINK_CONTROL3_REGLink Control 3 Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalsePERFORM_EQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr7661Perform Equalization.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP 00REQ_REQ_INT_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr7674Link Equalization Request Interrupt Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP 110x0RRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7681Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGLANE_ERR_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr77070x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_LANE_ERR_STATUS_REGLane Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseLANE_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr7698Lane Error Status Bits per Lane.For a description of this standard PCIe register field, see the PCI Express Specification.700x00R/W1CRSVDP_LANE_ERR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr7706Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGSPCIE_CAP_OFF_0CH_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr78460xCR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REGLane Equalization Control Register for lanes 1 and 0.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_SETDWC_pcie_wire_cpcie_usp_4x8.csr7723Downstream Port 8.0 GT/s Transmitter Preset 0.For a description of this standard PCIe register field, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_SETDWC_pcie_wire_cpcie_usp_4x8.csr7733Downstream Port 8.0 GT/s Receiver Preset Hint 0.For a description of this standard PCIe register field, see the PCI Express Specification.640x0RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr7740Reserved for future use.770x0RUSP_TX_PRESET0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_SETDWC_pcie_wire_cpcie_usp_4x8.csr7756Upstream Port 8.0 GT/s Transmitter Preset 0.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_SETDWC_pcie_wire_cpcie_usp_4x8.csr7772Upstream Port 8.0 GT/s Receiver Preset Hint 0.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr7779Reserved for future use.15150x0RDSP_TX_PRESET1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7789Downstream Port 8.0 GT/s Transmitter Preset 1.For a description of this standard PCIe register field, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7799Downstream Port 8.0 GT/s Receiver Preset Hint 1.For a description of this standard PCIe register field, see the PCI Express Specification.22200x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr7806Reserved for future use.23230x0RUSP_TX_PRESET1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7822Upstream Port 8.0 GT/s Transmitter Preset 1.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr7838Upstream Port 8.0 GT/s Receiver Preset Hint 1.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr7845Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGSPCIE_CAP_OFF_10H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr79900x10R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #2.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7867Downstream Port 8.0 GT/s Transmitter Preset2.For a description of this standard PCIe register, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7877Downstream Port 8.0 GT/s Receiver Preset Hint2.For a description of this standard PCIe register, see the PCI Express Specification.640x0RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr7884Reserved for future use.770x0RUSP_TX_PRESET2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7900Upstream Port 8.0 GT/s Transmitter Preset2.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_SETDWC_pcie_wire_cpcie_usp_4x8.csr7916Upstream Port 8.0 GT/s Receiver Preset Hint2.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr7923Reserved for future use.15150x0RDSP_TX_PRESET3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7933Downstream Port 8.0 GT/s Transmitter Preset3.For a description of this standard PCIe register, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7943Downstream Port 8.0 GT/s Receiver Preset Hint3.For a description of this standard PCIe register, see the PCI Express Specification.22200x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr7950Reserved for future use.23230x0RUSP_TX_PRESET3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7966Upstream Port 8.0 GT/s Transmitter Preset3.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_SETDWC_pcie_wire_cpcie_usp_4x8.csr7982Upstream Port 8.0 GT/s Receiver Preset Hint3.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr7989Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGSPCIE_CAP_OFF_14H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr81340x14R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #4.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_SETDWC_pcie_wire_cpcie_usp_4x8.csr8011Downstream Port 8.0 GT/s Transmitter Preset4.For a description of this standard PCIe register, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_SETDWC_pcie_wire_cpcie_usp_4x8.csr8021Downstream Port 8.0 GT/s Receiver Preset Hint4.For a description of this standard PCIe register, see the PCI Express Specification.640x0RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr8028Reserved for future use.770x0RUSP_TX_PRESET4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_SETDWC_pcie_wire_cpcie_usp_4x8.csr8044Upstream Port 8.0 GT/s Transmitter Preset4.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_SETDWC_pcie_wire_cpcie_usp_4x8.csr8060Upstream Port 8.0 GT/s Receiver Preset Hint4.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr8067Reserved for future use.15150x0RDSP_TX_PRESET5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_SETDWC_pcie_wire_cpcie_usp_4x8.csr8077Downstream Port 8.0 GT/s Transmitter Preset5.For a description of this standard PCIe register, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_SETDWC_pcie_wire_cpcie_usp_4x8.csr8087Downstream Port 8.0 GT/s Receiver Preset Hint5.For a description of this standard PCIe register, see the PCI Express Specification.22200x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr8094Reserved for future use.23230x0RUSP_TX_PRESET5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_SETDWC_pcie_wire_cpcie_usp_4x8.csr8110Upstream Port 8.0 GT/s Transmitter Preset5.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_SETDWC_pcie_wire_cpcie_usp_4x8.csr8126Upstream Port 8.0 GT/s Receiver Preset Hint5.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr8133Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGSPCIE_CAP_OFF_18H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr82780x18R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #6.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_SETDWC_pcie_wire_cpcie_usp_4x8.csr8155Downstream Port 8.0 GT/s Transmitter Preset6.For a description of this standard PCIe register, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_SETDWC_pcie_wire_cpcie_usp_4x8.csr8165Downstream Port 8.0 GT/s Receiver Preset Hint6.For a description of this standard PCIe register, see the PCI Express Specification.640x0RRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr8172Reserved for future use.770x0RUSP_TX_PRESET6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_SETDWC_pcie_wire_cpcie_usp_4x8.csr8188Upstream Port 8.0 GT/s Transmitter Preset6.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_SETDWC_pcie_wire_cpcie_usp_4x8.csr8204Upstream Port 8.0 GT/s Receiver Preset Hint6.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr8211Reserved for future use.15150x0RDSP_TX_PRESET7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_SETDWC_pcie_wire_cpcie_usp_4x8.csr8221Downstream Port 8.0 GT/s Transmitter Preset7.For a description of this standard PCIe register, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_SETDWC_pcie_wire_cpcie_usp_4x8.csr8231Downstream Port 8.0 GT/s Receiver Preset Hint7.For a description of this standard PCIe register, see the PCI Express Specification.22200x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr8238Reserved for future use.23230x0RUSP_TX_PRESET7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_SETDWC_pcie_wire_cpcie_usp_4x8.csr8254Upstream Port 8.0 GT/s Transmitter Preset7.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_SETDWC_pcie_wire_cpcie_usp_4x8.csr8270Upstream Port 8.0 GT/s Receiver Preset Hint7.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr8277Reserved for future use.31310x0RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAPPF0_PL16G_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr86980x1B8R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAPPhysical Layer 16.0 GT/s Extended Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGPL16G_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr83380x0R0x1e010026PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REGPhysical Layer 16.0 GT/s Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr8305PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0026RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr8321Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr8337Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x1e0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGPL16G_CAPABILITY_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr83520x4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_CAPABILITY_REG16.0 GT/s Capabilities Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr8351Reserved for future use.3100x00000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGPL16G_CONTROL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr83660x8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_CONTROL_REG16.0 GT/s Control Register .For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr8365Reserved for future use.3100x00000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGPL16G_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr84470xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_STATUS_REG16.0 GT/s Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEQ_16G_CPLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_SETDWC_pcie_wire_cpcie_usp_4x8.csr8385Equalization 16.0GT/s Complete.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.000x0REQ_16G_CPL_P1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_SETDWC_pcie_wire_cpcie_usp_4x8.csr8399Equalization 16.0GT/s Phase 1 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.110x0REQ_16G_CPL_P2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_SETDWC_pcie_wire_cpcie_usp_4x8.csr8413Equalization 16.0GT/s Phase 2 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.220x0REQ_16G_CPL_P3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_SETDWC_pcie_wire_cpcie_usp_4x8.csr8427Equalization 16.0GT/s Phase 3 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.330x0RLINK_EQ_16G_REQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr8438Link Equalization Request 16.0GT/s.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.440x0R/W1CRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr8446Reserved for future use.3150x0000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGPL16G_LC_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr84720x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG16.0 GT/s Local Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseLC_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr8463Local Data Parity Mismatch Status.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_LC_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr8471Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGPL16G_FIRST_RETIMER_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr84970x14R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG16.0 GT/s First Retimer Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseFIRST_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr8488First Retimer Data Parity Mismatch Status.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_FIRST_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr8496Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGPL16G_SECOND_RETIMER_DPAR_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr85230x18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG16.0 GT/s Second Retimer Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseSECOND_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr8514Second Retimer Data Parity Mismatch Status .For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_SECOND_RETIMER_DPAR_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr8522Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGPL16G_CAP_OFF_20H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr86100x20R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG16.0 GT/s Lane Equalization Control Register for Lane 0-3.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseDSP_16G_TX_PRESET0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_SETDWC_pcie_wire_cpcie_usp_4x8.csr8539Downstream Port 16.0 GT/s Transmitter Preset0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.300x0RUSP_16G_TX_PRESET0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_SETDWC_pcie_wire_cpcie_usp_4x8.csr8549Upstream Port 16.0 GT/s Transmitter Preset0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.740x0RDSP_16G_TX_PRESET1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_SETDWC_pcie_wire_cpcie_usp_4x8.csr8559Downstream Port 16.0 GT/s Transmitter Preset1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1180x0RUSP_16G_TX_PRESET1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_SETDWC_pcie_wire_cpcie_usp_4x8.csr8569Upstream Port 16.0 GT/s Transmitter Preset1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.15120x0RDSP_16G_TX_PRESET2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_SETDWC_pcie_wire_cpcie_usp_4x8.csr8579Downstream Port 16.0 GT/s Transmitter Preset2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.19160x0RUSP_16G_TX_PRESET2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_SETDWC_pcie_wire_cpcie_usp_4x8.csr8589Upstream Port 16.0 GT/s Transmitter Preset2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.23200x0RDSP_16G_TX_PRESET3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_SETDWC_pcie_wire_cpcie_usp_4x8.csr8599Downstream Port 16.0 GT/s Transmitter Preset3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.27240x0RUSP_16G_TX_PRESET3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_SETDWC_pcie_wire_cpcie_usp_4x8.csr8609Upstream Port 16.0 GT/s Transmitter Preset3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31280x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGPL16G_CAP_OFF_24H_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr86970x24R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG16.0 GT/s Lane Equalization Control Register for Lane 4-7.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseDSP_16G_TX_PRESET4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_SETDWC_pcie_wire_cpcie_usp_4x8.csr8626Downstream Port 16.0 GT/s Transmitter Preset4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.300x0RUSP_16G_TX_PRESET4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_SETDWC_pcie_wire_cpcie_usp_4x8.csr8636Upstream Port 16.0 GT/s Transmitter Preset4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.740x0RDSP_16G_TX_PRESET5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_SETDWC_pcie_wire_cpcie_usp_4x8.csr8646Downstream Port 16.0 GT/s Transmitter Preset5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1180x0RUSP_16G_TX_PRESET5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_SETDWC_pcie_wire_cpcie_usp_4x8.csr8656Upstream Port 16.0 GT/s Transmitter Preset5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.15120x0RDSP_16G_TX_PRESET6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_SETDWC_pcie_wire_cpcie_usp_4x8.csr8666Downstream Port 16.0 GT/s Transmitter Preset6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.19160x0RUSP_16G_TX_PRESET6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_SETDWC_pcie_wire_cpcie_usp_4x8.csr8676Upstream Port 16.0 GT/s Transmitter Preset6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.23200x0RDSP_16G_TX_PRESET7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_SETDWC_pcie_wire_cpcie_usp_4x8.csr8686Downstream Port 16.0 GT/s Transmitter Preset7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.27240x0RUSP_16G_TX_PRESET7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_SETDWC_pcie_wire_cpcie_usp_4x8.csr8696Upstream Port 16.0 GT/s Transmitter Preset7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31280x0RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAPPF0_MARGIN_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr96870x1E0R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAPMargining Extended Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGMARGIN_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr87570x0R0x20810027PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REGMargining Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr8724PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0027RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr8740Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr8756Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x208RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGMARGIN_PORT_CAPABILITIES_STATUS_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr88140x4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REGMargining Port Capabilities and Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseMARGINING_USES_DRIVER_SOFTWAREPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_SETDWC_pcie_wire_cpcie_usp_4x8.csr8779Margining uses Driver Software.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.000x0RRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr8786Reserved for future use.1510x0000RMARGINING_READYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_SETDWC_pcie_wire_cpcie_usp_4x8.csr8796Margining Ready.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.1616RMARGINING_SOFTWARE_READYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_SETDWC_pcie_wire_cpcie_usp_4x8.csr8806Margining Software Ready.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.1717RRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr8813Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGMARGIN_LANE_CNTRL_STATUS0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr89230x8R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REGMargining Lane Control and Status Register for Lane 0.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr8828Receiver Number for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr8838Margin Type for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr8848Usage Model for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr8856Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr8866Margin Payload for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr8878Receiver Number(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr8890Margin Type(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr8902Usage Model(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr8910Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr8922Margin Payload(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGMARGIN_LANE_CNTRL_STATUS1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr90320xCR/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REGMargining Lane Control and Status Register for Lane 1.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr8937Receiver Number for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr8947Margin Type for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr8957Usage Model for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr8965Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr8975Margin Payload for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr8987Receiver Number(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr8999Margin Type(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9011Usage Model(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr9019Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9031Margin Payload(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGMARGIN_LANE_CNTRL_STATUS2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr91410x10R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REGMargining Lane Control and Status Register for Lane 2.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr9046Receiver Number for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr9056Margin Type for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr9066Usage Model for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr9074Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr9084Margin Payload for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9096Receiver Number(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9108Margin Type(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9120Usage Model(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr9128Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9140Margin Payload(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGMARGIN_LANE_CNTRL_STATUS3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr92500x14R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REGMargining Lane Control and Status Register for Lane 3.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr9155Receiver Number for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr9165Margin Type for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr9175Usage Model for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr9183Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr9193Margin Payload for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9205Receiver Number(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9217Margin Type(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9229Usage Model(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr9237Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9249Margin Payload(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGMARGIN_LANE_CNTRL_STATUS4_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr93590x18R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REGMargining Lane Control and Status Register for Lane 4.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr9264Receiver Number for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr9274Margin Type for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr9284Usage Model for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr9292Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr9302Margin Payload for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9314Receiver Number(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9326Margin Type(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9338Usage Model(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr9346Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9358Margin Payload(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGMARGIN_LANE_CNTRL_STATUS5_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr94680x1CR/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REGMargining Lane Control and Status Register for Lane 5.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr9373Receiver Number for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr9383Margin Type for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr9393Usage Model for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr9401Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr9411Margin Payload for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9423Receiver Number(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9435Margin Type(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9447Usage Model(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr9455Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9467Margin Payload(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGMARGIN_LANE_CNTRL_STATUS6_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr95770x20R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REGMargining Lane Control and Status Register for Lane 6.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr9482Receiver Number for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr9492Margin Type for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr9502Usage Model for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr9510Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr9520Margin Payload for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9532Receiver Number(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9544Margin Type(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9556Usage Model(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr9564Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9576Margin Payload(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGMARGIN_LANE_CNTRL_STATUS7_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr96860x24R/W0x00009c38PE0_DWC_pcie_ctl_AXI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REGMargining Lane Control and Status Register for Lane 7.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr9591Receiver Number for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr9601Margin Type for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr9611Usage Model for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr9619Reserved for future use.770x0RMARGIN_PAYLOADPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr9629Margin Payload for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9641Receiver Number(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9653Margin Type(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9665Usage Model(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr9673Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr9685Margin Payload(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAPPF0_TPH_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr99700x208R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAPPF TLP Processing Hints Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGTPH_EXT_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr97460x0R0x29410017PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REGTPH Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCIE_EXT_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr9713TPH Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0017RTPH_REQ_CAP_VERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_SETDWC_pcie_wire_cpcie_usp_4x8.csr9729Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RTPH_REQ_NEXT_PTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_SETDWC_pcie_wire_cpcie_usp_4x8.csr9745Next Capability Pointer.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x294RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGTPH_REQ_CAP_REG_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr98850x4R0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_TPH_REQ_CAP_REG_REGTPH Requestor Capability Register.For a description of this standard PCIe register, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register.falsefalsefalsefalseTPH_REQ_NO_ST_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr9768No ST Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RTPH_REQ_CAP_INT_VECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_SETDWC_pcie_wire_cpcie_usp_4x8.csr9784Interrupt Vector Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.110x0RTPH_REQ_DEVICE_SPECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_SETDWC_pcie_wire_cpcie_usp_4x8.csr9800Device Specific Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.220x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr9807Reserved for future use.730x00RTPH_REQ_EXTENDED_TPHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_SETDWC_pcie_wire_cpcie_usp_4x8.csr9823Extended TPH Requester Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RTPH_REQ_CAP_ST_TABLE_LOC_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr9839ST Table Location Bit 0.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RTPH_REQ_CAP_ST_TABLE_LOC_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr9855ST Table Location Bit 1.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_SETDWC_pcie_wire_cpcie_usp_4x8.csr9862Reserved for future use.15110x00RTPH_REQ_CAP_ST_TABLE_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr9877ST Table Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26160x000RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr9884Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGTPH_REQ_CONTROL_REG_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr99300x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REGTPH Requestor Control Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseTPH_REQ_ST_MODE_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr9904ST Mode Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr9912Reserved for future use.730x00RTPH_REQ_CTRL_REQ_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr9921TPH Requester Enable Bit.For a description of this standard PCIe register field, see the PCI Express Base Specification.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_SETDWC_pcie_wire_cpcie_usp_4x8.csr9929Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0TPH_ST_TABLE_REG_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr99690xCR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_TPH_CAP_TPH_ST_TABLE_REG_0TPH ST Table Register 0.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseTPH_REQ_ST_TABLE_LOWER_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr9951ST Table 0 Lower Byte.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: this field is RW or Tie to 0 by table size configure - Dbi: this field is RW or Tie to 0 by table size configure 700x00R/WTPH_REQ_ST_TABLE_HIGHER_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr9968ST Table 0 Upper Byte.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: this field is RW or Tie to 0 by table size configure - Dbi: this field is RW or Tie to 0 by table size configure 1580x00R--31160x0rgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_LTR_CAPPF0_LTR_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr101220x294R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_LTR_CAPPF Latency Tolerance Reporting Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_LTR_CAP.LTR_LATENCY_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REGLTR_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr10036This register provides capbility ID, capability version and next offset value for LTR(Latency Tolerance Reporting).0x0R0x29c10018PE0_DWC_pcie_ctl_AXI_Slave_PF0_LTR_CAP_LTR_CAP_HDR_REGLTR Extended Capability Header.This register provides capbility ID, capability version and next offset value for LTR(Latency Tolerance Reporting).falsefalsefalsefalseCAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr10001LTR Extended Capacity ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.PCI Express Extended Capability for the LTR Extended Capability is 0018h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0018RCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr10018Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr10035Next Capability Offset.This field contains the offset to the next PCI Express Extended Capability structure or 000h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x29cRregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_LTR_CAP.LTR_LATENCY_REGLTR_LATENCY_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr10121This register indicates Latency scale and vlaue for Max Snoop and No-Snoop.0x4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_LTR_CAP_LTR_LATENCY_REGLTR Max Snoop and No-Snoop Latency Register.This register indicates Latency scale and vlaue for Max Snoop and No-Snoop.falsefalsefalsefalseMAX_SNOOP_LATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SETDWC_pcie_wire_cpcie_usp_4x8.csr10059Max Snoop Latency Value.Along with the Max Snoop LatencyScale field,this register specifies the maximum snoop latency that a device is permitted to request. Software should set this to the platform’s maximum supported latency or less.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 00 0000 0000b.900x000R/WMAX_SNOOP_LAT_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr10074Max Snoop Latency Scale.This register provides a scale for the value contained within the Max Snoop LatencyValue field. Encoding is the same as the LatencyScale fields in the LTR Message.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 000b.Hardware operation is undefined if software writes a Not Permitted value to this field.12100x0R/WRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_SETDWC_pcie_wire_cpcie_usp_4x8.csr10082Reserved for future use.15130x0RMAX_NO_SNOOP_LATPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SETDWC_pcie_wire_cpcie_usp_4x8.csr10097Max No-Snoop Latency Value.Along with the Max No-Snoop LatencyScale field, this register specifies the maximum no-snoop latency that a device is permitted to request. Software should set this to the platform’s maximum supported latency or less.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 00 0000 0000b.25160x000R/WMAX_NO_SNOOP_LAT_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr10112Max No-Snoop Latency Scale.This register provides a scale for the value contained within the Max No-Snoop LatencyValue field. Encoding is the same as the LatencyScale fields in the LTR Message.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 000b.Hardware operation is undefined if software writes a Not Permitted value to this field.28260x0R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr10120Reserved for future use.31290x0RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAPPF0_L1SUB_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr105670x29CR/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAPL1 Substates Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGL1SUB_CAP_HEADER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr10196L1 Substates Extended Capability Header provides capbility ID, capability version and next offset value for L1 Substates.0x0R0x2bc1001ePE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REGL1 Substates Extended Capability Header.This register provides capbility ID, capability version and next offset value for L1 Substates.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr10153L1SUB Extended Capability ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.Extended Capability ID for L1 PM Substates is 001Eh.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x001eRCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr10170Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr10195Next Capability Offset.This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities.For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x2bcRregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGL1SUB_CAPABILITY_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr10359This register provides extended capability of L1 Substates.0x4R0x00380a1fPE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REGL1 Substates Capability Register.This register provides extended capability of L1 Substates.falsefalsefalsefalseL1_2_PCIPM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr10215PCI-PM L12 Supported.When Set this bit indicates that PCI-PM L1.2 is supported.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 000x1RL1_1_PCIPM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr10228PCI-PM L11 Supported.When Set this bit indicates that PCI-PM L1.1 is supported, and must be Set by all Ports implementing L1 PM Substates.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 110x1RL1_2_ASPM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr10240ASPM L12 Supported.When Set this bit indicates that ASPM L1.2 is supported.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 220x1RL1_1_ASPM_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr10252ASPM L11 Supported.When Set this bit indicates that ASPM L1.1 is supported.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 330x1RL1_PMSUB_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr10265L1 PM Substates ECN Supported.When Set this bit indicates that this Port supports L1 PM Substates.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 440x1RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr10272Reserved for future use.750x0RCOMM_MODE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr10291Port Common Mode Restore Time.Time (in us) required for this Port to re-establish common mode.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 1580x0aRPWR_ON_SCALE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr10318Port T Power On Scale.Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register.Range of values are given below.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 17160x0RfalsetruefalseReserved0x3Reserved.RSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr10325Reserved for future use.18180x0RPWR_ON_VALUE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr10351Port T Power On Value.Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.The value of Port T_POWER_ON is calculated by multiplying the value in this field by the scale value in the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register. Default value is 00101b.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 23190x07RRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr10358Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGL1SUB_CONTROL1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr10482This register provides Controls to extended capability.0x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAP_L1SUB_CONTROL1_REGL1 Substates Control 1 Register.This register provides Controls to extended capability.falsefalsefalsefalseL1_2_PCIPM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr10375PCI-PM L12 Enable.When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.000x0R/WL1_1_PCIPM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr10384PCI-PM L11 Enable.When Set this bit enables PCI-PM L1.1. Default value is 0b.110x0R/WL1_2_ASPM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr10394ASPM L12 Enable.When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.220x0R/WL1_1_ASPM_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr10404ASPM L11 Enable.When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.330x0R/WRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr10412Reserved for future use.740x0RT_COMMON_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr10432Common Mode Restore Time.Sets value of TCOMMONMODE (in μs), which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports.Default value is implementation specific.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RW : RSVDP 1580x00RL1_2_TH_VALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SETDWC_pcie_wire_cpcie_usp_4x8.csr10452LTR L12 Threshold Value.Along with the LTR_L1.2_THRESHOLD_Scale, this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b.Required for all Ports for which the ASPM L12 Supported bit is Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP 25160x000R/WRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_SETDWC_pcie_wire_cpcie_usp_4x8.csr10460Reserved for future use.28260x0RL1_2_TH_SCAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SETDWC_pcie_wire_cpcie_usp_4x8.csr10481LTR L12 Threshold Scale.This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field.Required for all Ports Ports for which the ASPM L12 Supported bit is Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP 31290x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGL1SUB_CONTROL2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr10566This register provides Controls to extended capability.0xCR/W0x00000028PE0_DWC_pcie_ctl_AXI_Slave_PF0_L1SUB_CAP_L1SUB_CONTROL2_REGL1 Substates Control 2 Register.This register provides Controls to extended capability.falsefalsefalsefalseT_POWER_ON_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr10520T Power On Scale.Specifies the scale used for T_POWER_ON Value.Range of values are given below.Required for all Ports that support L1.2, otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear.The Port behavior is undefined if this field is modified when either the ASPM L1.2 Enable and/or PCI-PM L1.2 Enable bit(s) are Set.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 100x0R/WfalsetruefalseReserved0x3Reserved.RSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr10528Reserved for future use.220x0RT_POWER_ON_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr10557T Power On Value.Along with the T_POWER_ON Scale sets the minimum amount of time (in μs) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b.T_POWER_ON is calculated by multiplying the value in this field by the value in the T_POWER_ON Scale field.Required for all Ports that support L1.2, otherwise this field is of type RsvdP.This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear.The Port behavior is undefined if this field is modified when either the ASPM L1.2 Enable and/or PCI-PM L1.2 Enable bit(s) are Set.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 730x05R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr10565Reserved for future use.3180x000000RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_LNR_CAPPF0_LNR_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr107430x2BCR/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_LNR_CAPPF LNR Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFFLNR_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr106260x0R0x2c41001cPE0_DWC_pcie_ctl_AXI_Slave_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFFLNR Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseLNR_EXT_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr10593PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x001cRLNR_CAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr10609Capability Verison.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RLNR_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr10625Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x2c4RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFFLNR_CAP_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr107420x4R/W0x1f000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_LNR_CAP_LNR_CAP_CONTROL_OFFLNR Control Register and Capability Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseLNR_64_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr10648LNR-64 Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.000x0RLNR_128_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr10665LNR-128 Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.110x0RRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr10673Reserved for future use.720x00RLNR_REGISTRATION_MAXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_SETDWC_pcie_wire_cpcie_usp_4x8.csr10690LNR Registration Max.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1280x00RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_SETDWC_pcie_wire_cpcie_usp_4x8.csr10698Reserved for future use.15130x0RLNR_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr10707LNR Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0R/WLNR_CLSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_SETDWC_pcie_wire_cpcie_usp_4x8.csr10716LNR CLS.For a description of this standard PCIe register field, see the PCI Express Base Specification.17170x0R/WRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr10724Reserved for future use.23180x00RLNR_REGISTRATION_LIMITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr10733LNR Registration Limit.For a description of this standard PCIe register field, see the PCI Express Base Specification.28240x1fR/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr10741Reserved for future use.31290x0RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAPPF0_RAS_DES_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr139830x2C4R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAPRAS D.E.S. Capability Structure (VSEC)registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGRAS_DES_CAP_HEADER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr108020x0R0x3c41000bPE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REGVendor-Specific Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseEXTENDED_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr10769PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x000bRCAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr10785Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr10801Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x3c4RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGVENDOR_SPECIFIC_HEADER_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr108360x4R0x10040002PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REGVendor-Specific Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVSEC_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr10817VSEC ID.For a description of this standard PCIe register field, see the PCI Express Specification.1500x0002RVSEC_REVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_SETDWC_pcie_wire_cpcie_usp_4x8.csr10826VSEC Rev.For a description of this standard PCIe register field, see the PCI Express Specification.19160x4RVSEC_LENGTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr10835VSEC Length.For a description of this standard PCIe register field, see the PCI Express Specification.31200x100RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGEVENT_COUNTER_CONTROL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr109830x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REGEvent Counter Control.This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG viewport register. - Setting the EVENT_COUNTER_ENABLE field in this register enables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Setting the EVENT_COUNTER_CLEAR field in this register clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Reading the EVENT_COUNTER_STATUS field in this register returns the Enable status of the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.falsefalsefalsefalseEVENT_COUNTER_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_SETDWC_pcie_wire_cpcie_usp_4x8.csr10877Event Counter Clear.Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.You can clear the value of a specific Event Counter by writing the 'per clear' code and you can clear all event counters at once by writing the 'all clear' code.The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11: all clear - Other: reserved100x0WEVENT_COUNTER_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr10903Event Counter Enable.Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.By default, all event counters are disabled.You can enable/disable a specific Event Counter by writing the 'per event off' or 'per event on' codes.You can enable/disable all event counters by writing the 'all on' or 'all off' codes.The read value is always '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no change - 101: all off - 110: no change - 111: all on420x0WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr10911Reserved for future use.650x0REVENT_COUNTER_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr10926Event Counter Status.This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECTNote: This register field is sticky.770x0REVENT_COUNTER_LANE_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr10943Event Counter Lane Select.This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr10951Reserved for future use.15120x0REVENT_COUNTER_EVENT_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr10974Event Counter Data Select.This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the GroupFor example: - 0x000: Ebuf Overflow - 0x001: Ebuf Underrun - .. - 0x700: Tx Memory Write - 0x713: Rx Message TLPFor detailed definitions of Group number and Event number, see the RAS DES chapter in the Databook.Note: This register field is sticky.27160x000R/WRSVDP_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_SETDWC_pcie_wire_cpcie_usp_4x8.csr10982Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGEVENT_COUNTER_DATA_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr110080xCR0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REGEvent Counter Data.This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REGFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEVENT_COUNTER_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_SETDWC_pcie_wire_cpcie_usp_4x8.csr11007Event Counter Data.This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REGNote: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGTIME_BASED_ANALYSIS_CONTROL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr111240x10R/W0x00000100PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REGTime-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIMER_STARTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr11032Timer Start. - 1: Start/Restart - 0: StopThis bit will be cleared automatically when the measurement is finished.Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr11040Reserved for future use.710x00RTIME_BASED_DURATION_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr11062Time-based Duration Select.Selects the duration of time-based analysis.When "manual control" is selected and TIMER_START is set to '1', this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1: 1ms - 0x2: 10ms - 0x3: 100ms - 0x4: 1s - 0x5: 2s - 0x6: 4s - 0xff: 4us (Debug purpose) - Else: ReservedNote: This register field is sticky.1580x01R/WRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr11070Reserved for future use.23160x00RTIME_BASED_REPORT_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr11123Time-based Report Select.Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT), and returned in TIME_BASED_ANALYSIS_DATA.Each type of data is measured using one of three types of units: - Core_clk Cycles for 2.5GT/s, 5.0GT/s, 8.0GT/s, 16.0GT/s, 32GT/s. Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x00] * TIME_BASED_ANALYSIS_DATA - Aux_clk Cycles. Total time in ps is [Period of platform specific clock] * TIME_BASED_ANALYSIS_DATA - Core_clk Cycles for 20GT/s, 25GT/s (CCIX ESM data rate). Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x10] * TIME_BASED_ANALYSIS_DATA - Data Bytes. Actual amount of bytes is 16 * TIME_BASED_ANALYSIS_DATACore_clk Cycles for 2.5GT/s, 5.0GT/s, 8.0GT/s, 16.0GT/s, 32GT/s - 0x00: Duration of 1 cycle - 0x01: TxL0s - 0x02: RxL0s - 0x03: L0 - 0x04: L1 - 0x07: Configuration/Recovery - 0x08: TxL0s and RxL0sAux_clk Cycles - 0x05: L1.1 - 0x06: L1.2 - 0x09: L1 auxCore_clk Cycles for 20GT/s, 25GT/s (CCIX ESM data rate) - 0x10: Duration of 1 cycle - 0x11: TxL0s - 0x12: RxL0s - 0x13: L0 - 0x14: L1 - 0x17: Configuration/Recovery - 0x18: TxL0s and RxL0sData Bytes - 0x20: Tx PCIe TLP data payload Bytes - 0x21: Rx PCIe TLP data payload Bytes - 0x22: Tx CCIX TLP data payload Bytes - 0x23: Rx CCIX TLP data payload Bytes - Else: RsvdNote: This register field is sticky.31240x00R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGTIME_BASED_ANALYSIS_DATA_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr111510x14R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REGTime-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state.This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIME_BASED_ANALYSIS_DATAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_SETDWC_pcie_wire_cpcie_usp_4x8.csr11150Time Based Analysis Data.This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.The results are cleared when next measurement starts.Note: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGTIME_BASED_ANALYSIS_DATA_63_32_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr111720x18R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REGUpper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIME_BASED_ANALYSIS_DATA_63_32PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_SETDWC_pcie_wire_cpcie_usp_4x8.csr11171Upper 32 bits of Time Based Analysis Data.Note: This register field is sticky.3100x00000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGEINJ_ENABLE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr113090x30R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ_ENABLE_REGError Injection Enable.Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1: Sequence Number Error: EINJ1_SEQNUM_REG - 2: DLLP Error: EINJ2_DLLP_REG - 3: Symbol DataK Mask Error or Sync Header Error: EINJ3_SYMBOL_REG - 4: FC Credit Update Error: EINJ4_FC_REG - 5: TLP Duplicate/Nullify Error: EINJ5_SP_TLP_REG - 6: Specific TLP Error: EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REGAfter the errors have been inserted by controller, it will clear each bit here.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_INJECTION0_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr11205Error Injection0 Enable (CRC Error).Enables insertion of errors into various CRC.For more details, see the EINJ0_CRC_REG register.Note: This register field is sticky.000x0R/WERROR_INJECTION1_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr11219Error Injection1 Enable (Sequence Number Error).Enables insertion of errors into sequence numbers.For more details, see the EINJ1_SEQNUM_REG register.Note: This register field is sticky.110x0R/WERROR_INJECTION2_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr11233Error Injection2 Enable (DLLP Error).Enables insertion of DLLP errors.For more details, see the EINJ2_DLLP_REG register.Note: This register field is sticky.220x0R/WERROR_INJECTION3_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr11249Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error).Enables DataK masking of special symbols or the breaking of the sync header.For more details, see the EINJ3_SYMBOL_REG register.Note: This register field is sticky.330x0R/WERROR_INJECTION4_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr11263Error Injection4 Enable (FC Credit Update Error).Enables insertion of errors into UpdateFCs.For more details, see the EINJ4_FC_REG register.Note: This register field is sticky.440x0R/WERROR_INJECTION5_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr11277Error Injection5 Enable (TLP Duplicate/Nullify Error).Enables insertion of duplicate/nullified TLPs.For more details, see the EINJ5_SP_TLP_REG register.Note: This register field is sticky.550x0R/WERROR_INJECTION6_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr11300Error Injection6 Enable (Specific TLP Error).Enables insertion of errors into the packets that you select.You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT =0.You can set this bit to '1' when you have disabled the address translation by setting ADDR_TRANSLATION_SUPPORT_EN=0.For more details, see the EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG registers.Note: This register field is sticky.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr11308Reserved for future use.3170x0000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGEINJ0_CRC_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr113790x34R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ0_CRC_REGError Injection Control 0 (CRC Error).Controls the insertion of errors into the CRC, and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link Retry starts. - 16-bit CRC of ACK/NAK DLLPs. Bad DLLP occurs at the receiver side; Replay NUM Rollover occurs. - 16-bit CRC of UpdateFC DLLPs. Error insertion continues for the specific time; LTSSM transitions to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - ECRC. If ECRC check is enabled, ECRC error is detected at the receiver side. - FCRC. Framing error will be detected, TLP is discarded, and the LTSSM transitions to Recovery state. - Parity of TSOS. Error insertion continues for the specific time; LTSSM Recovery/Configuration timeout will occur. - Parity of SKPOS. Lane error will be detected at the receiver side.falsefalsefalsefalseEINJ0_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr11347Error injection count.Indicates the number of errors.This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the counter value is 0x00 and ERROR_INJECTION0_ENABLE=1, the errors are inserted until ERROR_INJECTION0_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ0_CRC_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr11370Error injection type.Selects the type of CRC error to be inserted.Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC error injection - 0100b: TLP's FCRC error injection (128b/130b) - 0101b: Parity error of TSOS (128b/130b) - 0110b: Parity error of SKPOS (128b/130b)Rx Path - 1000b: LCRC error injection - 1011b: ECRC error injection - Others: ReservedNote: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr11378Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGEINJ1_SEQNUM_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr114770x38R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REGError Injection Control 1 (Sequence Number Error).Controls the sequence number of the specific TLPs and ACK/NAK DLLPs.Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: - ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 4096 >= 2048TLP is treated as Duplicate TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ - (NEXT_RCV_SEQ - Sequence Number) mod 4096 <= 2048TLP is treated as Bad TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ and - (NEXT_RCV_SEQ - Sequence Number) mod 4096 > 2048falsefalsefalsefalseEINJ1_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr11414Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION1_ENABLE=1, the errors are inserted until ERROR_INJECTION1_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ1_SEQNUM_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr11426Sequence number type.Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# ErrorNote: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr11434Reserved for future use.1590x00REINJ1_BAD_SEQNUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_SETDWC_pcie_wire_cpcie_usp_4x8.csr11468Bad sequence number.Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095For example: - Set Type, SEQ# and Count -- EINJ1_SEQNUM_TYPE =0 (Insert errors into new TLPs) -- EINJ1_BAD_SEQNUM =0x1FFD (represents -3) -- EINJ1_COUNT =1 - Enable Error Injection -- ERROR_INJECTION1_ENABLE =1 - Send a TLP From the Core's Application Interface -- Assume SEQ#5 is given to the TLP. - The SEQ# is Changed to #2 by the Error Injection Function in Layer2. -- 5 + (-3) = 2 - The TLP with SEQ#2 is Transmitted to PCIe Link.Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr11476Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGEINJ2_DLLP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr115370x3CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ2_DLLP_REGError Injection Control 2 (DLLP Error).Controls the transmission of DLLPs and inserts the following errors: - If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the transmitter of the TLPs and then Data Link Retry will occur. - If "Update FC DLLP's transmission block" is selected, LTSSM will transition to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - If "Always Transmission for NAK DLLP" is selected, Data Link Retry will occur at the transmitter of the TLPs. Furthermore, Replay NUM Rollover will occur when the transmitter has been requested four times to send the TLP with the same sequence number.falsefalsefalsefalseEINJ2_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr11514Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION2_ENABLE =1, the errors are inserted until ERROR_INJECTION2_ENABLE is set to '0'.This register is affected only when EINJ2_DLLP_TYPE =2'10b.Note: This register field is sticky.700x00R/WEINJ2_DLLP_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr11528DLLP Type.Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: ReservedNote: This register field is sticky.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_SETDWC_pcie_wire_cpcie_usp_4x8.csr11536Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGEINJ3_SYMBOL_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr115970x40R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REGError Injection Control 3 (Symbol Error).When 8b/10b encoding is used, this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeout of the LTSSM. - If END/EDB/STP/SDP is selected, TLP/DLLP will be discarded at the receiver side.When 128b/130b encoding is used, this register controls error insertion into the sync-header.falsefalsefalsefalseEINJ3_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr11565Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION3_ENABLE =1, the errors are inserted until ERROR_INJECTION3_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ3_SYMBOL_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr11588Error Type.8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set) - 011b: COM/FTS(FTS Order set) - 100b: COM/IDL(E-Idle Order set) - 101b: END/EDB Symbol - 110b: STP/SDP Symbol - 111b: COM/SKP(SKP Order set)128b/130b encoding - Change sync header. - 000b: Invert sync header - Others: ReservedNote: This register field is sticky.1080x0R/WRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_SETDWC_pcie_wire_cpcie_usp_4x8.csr11596Reserved for future use.31110x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGEINJ4_FC_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr117020x44R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ4_FC_REGError Injection Control 4 (FC Credit Error).Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Posted TLP Data credit - Non-Posted TLP Data credit - Completion TLP Data creditThese errors are not correctable while error insertion is enabled. Receiver buffer overflow error might occur.falsefalsefalsefalseEINJ4_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr11628Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION4_ENABLE =1, the errors are inserted until ERROR_INJECTION4_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ4_UPDFC_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr11646Update-FC type.Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit value control - 101b: Non-Posted TLP Data Credit value control - 110b: Completion TLP Data Credit value control - 111b: ReservedNote: This register field is sticky.1080x0R/WRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_SETDWC_pcie_wire_cpcie_usp_4x8.csr11654Reserved for future use.11110x0REINJ4_VC_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr11665VC Number.Indicates target VC Number.Note: This register field is sticky.14120x0R/WRSVDP_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr11673Reserved for future use.15150x0REINJ4_BAD_UPDFC_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr11693Bad update-FC credit value.Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr11701Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGEINJ5_SP_TLP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr117590x48R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REGError Injection Control 5 (Specific TLP Error).Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP, the controller initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TLPs will be duplicate TLPs at the receiver side. - For Nullified TLP, the TLPs that the controller transmits are changed into nullified TLPs and the original TLPs are stored in the retry buffer. The receiver of these TLPs will detect the lack of seq# and send NAK DLLP at the next TLP. Then the original TLPs are sent from retry buffer and the data controls are recovered. For 128 bit controller or more than 128 bit, the controller inserts errors the number of times of EINJ5_COUNT but doesn't ensure that the errors are continuously inserted into TLPs.falsefalsefalsefalseEINJ5_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr11736Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION5_ENABLE =1, the errors are inserted until ERROR_INJECTION5_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ5_SPECIFIED_TLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_SETDWC_pcie_wire_cpcie_usp_4x8.csr11750Specified TLP.Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer).Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr11758Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGEINJ6_COMPARE_POINT_H0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr117970x4CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REGError Injection Control 6 (Compare Point Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_SETDWC_pcie_wire_cpcie_usp_4x8.csr11796Packet Compare Point: 1st DWORD.Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGEINJ6_COMPARE_POINT_H1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr118350x50R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REGError Injection Control 6 (Compare Point Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_SETDWC_pcie_wire_cpcie_usp_4x8.csr11834Packet Compare Point: 2nd DWORD.Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGEINJ6_COMPARE_POINT_H2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr118710x54R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REGError Injection Control 6 (Compare Point Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_SETDWC_pcie_wire_cpcie_usp_4x8.csr11870Packet Compare Point: 3rd DWORD.Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGEINJ6_COMPARE_POINT_H3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr119090x58R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REGError Injection Control 6 (Compare Point Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_SETDWC_pcie_wire_cpcie_usp_4x8.csr11908Packet Compare Point: 4th DWORD.Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGEINJ6_COMPARE_VALUE_H0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr119430x5CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REGError Injection Control 6 (Compare Value Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_SETDWC_pcie_wire_cpcie_usp_4x8.csr11942Packet Compare Value: 1st DWORD.Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGEINJ6_COMPARE_VALUE_H1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr119770x60R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REGError Injection Control 6 (Compare Value Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_SETDWC_pcie_wire_cpcie_usp_4x8.csr11976Packet Compare Value: 2nd DWORD.Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGEINJ6_COMPARE_VALUE_H2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr120110x64R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REGError Injection Control 6 (Compare Value Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_SETDWC_pcie_wire_cpcie_usp_4x8.csr12010Packet Compare Value: 3rd DWORD.Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGEINJ6_COMPARE_VALUE_H3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr120450x68R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REGError Injection Control 6 (Compare Value Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_SETDWC_pcie_wire_cpcie_usp_4x8.csr12044Packet Compare Value: 4th DWORD.Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGEINJ6_CHANGE_POINT_H0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr120770x6CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REGError Injection Control 6 (Change Point Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_SETDWC_pcie_wire_cpcie_usp_4x8.csr12076Packet Change Point: 1st DWORD.Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGEINJ6_CHANGE_POINT_H1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr121090x70R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REGError Injection Control 6 (Change Point Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_SETDWC_pcie_wire_cpcie_usp_4x8.csr12108Packet Change Point: 2nd DWORD.Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGEINJ6_CHANGE_POINT_H2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr121410x74R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REGError Injection Control 6 (Change Point Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_SETDWC_pcie_wire_cpcie_usp_4x8.csr12140Packet Change Point: 3rd DWORD.Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGEINJ6_CHANGE_POINT_H3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr121730x78R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REGError Injection Control 6 (Change Point Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_SETDWC_pcie_wire_cpcie_usp_4x8.csr12172Packet Change Point: 4th DWORD.Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGEINJ6_CHANGE_VALUE_H0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr122080x7CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REGError Injection Control 6 (Change Value Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_SETDWC_pcie_wire_cpcie_usp_4x8.csr12207Packet Change Value: 1st DWORD.Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGEINJ6_CHANGE_VALUE_H1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr122430x80R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REGError Injection Control 6 (Change Value Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_SETDWC_pcie_wire_cpcie_usp_4x8.csr12242Packet Change Value: 2nd DWORD.Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGEINJ6_CHANGE_VALUE_H2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr122780x84R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REGError Injection Control 6 (Change Value Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_SETDWC_pcie_wire_cpcie_usp_4x8.csr12277Packet Change Value: 3rd DWORD.Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGEINJ6_CHANGE_VALUE_H3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr123130x88R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REGError Injection Control 6 (Change Value Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_SETDWC_pcie_wire_cpcie_usp_4x8.csr12312Packet Change Value: 4th DWORD.Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGEINJ6_TLP_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr123940x8CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_EINJ6_TLP_REGError Injection Control 6 (Packet Error).The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the this register.The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the this register.Only applies when EINJ6_INVERTED_CONTROL in this register =0.The TLP into that errors are injected will not arrive at the transaction layer of the remote device when all of the following conditions are true. - Using 128b/130b encoding - Injecting errors into TLP Length field / TLP digest bitfalsefalsefalsefalseEINJ6_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr12357Error Injection Count.Indicates the number of errors to insert.This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION6_ENABLE=1, errors are inserted until ERROR_INJECTION6_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ6_INVERTED_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_SETDWC_pcie_wire_cpcie_usp_4x8.csr12370Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3].Note: This register field is sticky.880x0R/WEINJ6_PACKET_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr12385Packet type.Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: ReservedNote: This register field is sticky.1190x0R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr12393Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGSD_CONTROL1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr124910xA0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_CONTROL1_REGSilicon Debug Control 1.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_DETECT_LANEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_SETDWC_pcie_wire_cpcie_usp_4x8.csr12417Force Detect Lane.When the FORCE_DETECT_LANE_EN field is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15Note: This register field is sticky.1500x0000R/WFORCE_DETECT_LANE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr12431Force Detect Lane Enable.When this bit is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE.Note: This register field is sticky.16160x0R/WRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_SETDWC_pcie_wire_cpcie_usp_4x8.csr12439Reserved for future use.19170x0RTX_EIOS_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_SETDWC_pcie_wire_cpcie_usp_4x8.csr12464Number of Tx EIOS.This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification.2.5GT/s, 8.0GT/s or higher: - 0x0: 1 - 0x1: 4 - 0x2: 8 - 0x3: 165.0GT/s: - 0x0: 2 - 0x1: 8 - 0x2: 16 - 0x3: 32Note: This register field is sticky.21200x0R/WLOW_POWER_INTERVALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_SETDWC_pcie_wire_cpcie_usp_4x8.csr12482Low Power Entry Interval Time.Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - 0x3: 640nsNote: This register field is sticky.23220x0R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr12490Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGSD_CONTROL2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr126140xA4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_CONTROL2_REGSilicon Debug Control 2.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseHOLD_LTSSMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_SETDWC_pcie_wire_cpcie_usp_4x8.csr12509Hold and Release LTSSM.For as long as this register is '1', the controller stays in the current LTSSM.Note: This register field is sticky.000x0R/WRECOVERY_REQUESTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_SETDWC_pcie_wire_cpcie_usp_4x8.csr12522Recovery Request.When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization.110x0WNOACK_FORCE_LINKDOWNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_SETDWC_pcie_wire_cpcie_usp_4x8.csr12536Force LinkDown.When this bit is set and the controller detects REPLY_NUM rolling over 4 times, the LTSSM transitions to Detect State.Note: This register field is sticky.220x0R/WRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr12544Reserved for future use.730x00RDIRECT_RECIDLE_TO_CONFIGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_SETDWC_pcie_wire_cpcie_usp_4x8.csr12557Direct Recovery.Idle to Configuration.When this bit is set and the LTSSM is in Recovery Idle State, the LTSSM transitions to Configuration state.Note: This register field is sticky.880x0R/WDIRECT_POLCOMP_TO_DETECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr12570Direct Polling.Compliance to Detect.When this bit is set and the LTSSM is in Polling Compliance State, the LTSSM transitions to Detect state.Note: This register field is sticky.990x0R/WDIRECT_LPBKSLV_TO_EXITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr12584Direct Loopback Slave To Exit.When this bit is set and the LTSSM is in Loopback Slave Active State, the LTSSM transitions to Loopback Slave Exit state.Note: This register field is sticky.10100x0R/WRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_SETDWC_pcie_wire_cpcie_usp_4x8.csr12592Reserved for future use.15110x00RFRAMING_ERR_RECOVERY_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr12605Framing Error Recovery Disable.This bit disables a transition to Recovery state when a Framing Error is occurred.Note: This register field is sticky.16160x0R/WRSVDP_17PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_SETDWC_pcie_wire_cpcie_usp_4x8.csr12613Reserved for future use.31170x0000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGSD_STATUS_L1LANE_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr127460xB0R/W0x00180000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REGSilicon Debug Status(Layer1 Per-lane).This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REGFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseLANE_SELECTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr12639Lane Select.Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.300x0R/WRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr12647Reserved for future use.1540x000RPIPE_RXPOLARITYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr12662PIPE:RxPolarity.Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT).Note: This register field is sticky.16160x0RPIPE_DETECT_LANEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_SETDWC_pcie_wire_cpcie_usp_4x8.csr12677PIPE:Detect Lane.Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT).Note: This register field is sticky.17170x0RPIPE_RXVALIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_SETDWC_pcie_wire_cpcie_usp_4x8.csr12692PIPE:RxValid.Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT).Note: This register field is sticky.18180x0RPIPE_RXELECIDLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr12707PIPE:RxElecIdle.Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT).Note: This register field is sticky.19190x1RPIPE_TXELECIDLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr12722PIPE:TxElecIdle.Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT).Note: This register field is sticky.20200x1RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_SETDWC_pcie_wire_cpcie_usp_4x8.csr12730Reserved for future use.23210x0RDESKEW_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr12745Deskew Pointer.Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT).Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGSD_STATUS_L1LTSSM_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr128950xB4R/W0x00000200PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REGSilicon Debug Status(Layer1 LTSSM).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFRAMING_ERR_PTRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_SETDWC_pcie_wire_cpcie_usp_4x8.csr12815First Framing Error Pointer.Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1.Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When current token was not a valid EDB token and previous token was an EDB. (128/256 bit controller only) - 03h: When SDP token was received but not expected. (128 bit & (x8 | x16) controller only) - 04h: When STP token was received but not expected. (128 bit & (x8 | x16) controller only) - 05h: When EDS token was expected but not received or whenever an EDS token was received but not expected. - 06h: When a framing error was detected in the deskew block while a packet has been in progress in token_finder.Received Unexpected STP Token - 11h: When Framing CRC in STP token did not match - 12h: When Framing Parity in STP token did not match. - 13h: When Framing TLP Length in STP token was smaller than 5 DWORDs.Received Unexpected Block - 21h: When Receiving an OS Block following SDS in Datastream state - 22h: When Data Block followed by OS Block different from SKP, EI, EIE in Datastream state - 23h: When Block with an undefined Block Type in Datastream state - 24h: When Data Stream without data over three cycles in Datastream state - 25h: When OS Block during Data Stream in Datastream state - 26h: When RxStatus Error was detected in Datastream state - 27h: When Not all active lanes receiving SKP OS starting at same cycle time in SKPOS state - 28h: When a 2-Block timeout occurs for SKP OS in SKPOS state - 29h: When Receiving consecutive OS Blocks within a Data Stream in SKPOS state - 2Ah: When Phy status error was detected in SKPOS state - 2Bh: When Not all active lanes receiving EIOS starting at same cycle time in EIOS state - 2Ch: When At least one Symbol from the first 4 Symbols is not EIOS Symbol in EIOS state (CX_NB=2 only) - 2Dh: When Not all active lanes receiving EIEOS starting at same cycle time in EIEOS state - 2Eh: When Not full 16 eieos symbols are received in EIEOS stateAll other values not listed above are Reserved.Note: This register field is sticky.600x00RFRAMING_ERRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_SETDWC_pcie_wire_cpcie_usp_4x8.csr12826Framing Error.Indicates Framing Error detection status.770x0R/W1CPIPE_POWER_DOWNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_SETDWC_pcie_wire_cpcie_usp_4x8.csr12840PIPE:PowerDown.Indicates PIPE PowerDown signal.Note: This register field is sticky.1080x2RRSVDP_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_SETDWC_pcie_wire_cpcie_usp_4x8.csr12848Reserved for future use.14110x0RLANE_REVERSALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_SETDWC_pcie_wire_cpcie_usp_4x8.csr12864Lane Reversal Operation.Receiver detected lane reversal.This field is only valid in the L0 LTSSM state.Note: This register field is sticky.15150x0RLTSSM_VARIABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr12894LTSSM Variable.Indicates internal LTSSM variables defined in the PCI Express Base Specification.C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if both ports advertised the UpConfigure capability in the last Config.Complete. - 4: select_deemphasis - 5: start_equalization_w_preset - 6: equalization_done_8GT_data_rate - 7: equalization_done_16GT_data_rate - 15:8: idle_to_rlock_transitionedM-PCIe Mode: - 0: idle_to_recovery - 1: recovery_to_configurationNote: This register field is sticky.31160x0000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGSD_STATUS_PM_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr130360xB8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_PM_REGSilicon Debug Status(PM).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseINTERNAL_PM_MSTATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_SETDWC_pcie_wire_cpcie_usp_4x8.csr12937Internal PM State(Master).Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah: L1_WAIT_LAST_TLP_ACK - 0Bh: L1_WAIT_PMDLLP_ACK - 0Ch: L1_LINK_ENTR_L1 - 0Dh: L1_EXIT - 0Fh: PREP_4L1 - 10h: L23_BLOCK_TLP - 11h: L23_WAIT_LAST_TLP_ACK - 12h: L23_WAIT_PMDLLP_ACK - 13h: L23_ENTR_L23 - 14h: L23RDY - 15h: PREP_4L23 - 16h: L23RDY_WAIT4ALIVE - 17h: L0S_BLOCK_TLP - 18h: WAIT_LAST_PMDLLP - 19h: WAIT_DSTATE_UPDATENote: This register field is sticky.400x00RRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr12945Reserved for future use.750x0RINTERNAL_PM_SSTATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_SETDWC_pcie_wire_cpcie_usp_4x8.csr12972Internal PM State(Slave).Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h: S_L1_EXIT - 8h: S_L23RDY - 9h: S_LINK_ENTR_L23 - Ah: S_L23RDY_WAIT4ALIVE - Bh: S_ACK_WAIT4IDLE - Ch: S_WAIT_LAST_PMDLLPNote: This register field is sticky.1180x0RPME_RESEND_FLAGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_SETDWC_pcie_wire_cpcie_usp_4x8.csr12986PME Re-send flag.When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent.12120x0R/W1CL1SUB_STATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_SETDWC_pcie_wire_cpcie_usp_4x8.csr13012L1Sub State.Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check clkreq_in_n is de-asserted for t_power_off time (only for L1.2, reduces to one cycle for L1.1) - 5h: S_L1_N : L1 substate, turn off txcommonmode circuits (L1.2 only) and rx electrical idle detection circuits - 6h: S_L1_N_EXIT : locally/remotely initiated exit, assert pclkreq, wait for pclkack - 7h: S_L1_N_ABORT : wait for pclkack when aborting an attempt to enter L1_NNote: This register field is sticky.15130x0RLATCHED_NFTSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_SETDWC_pcie_wire_cpcie_usp_4x8.csr13027Latched N_FTS.Indicates the value of N_FTS in the received TS Ordered Sets from the Link PartnerNote: This register field is sticky.23160x00RRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr13035Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGSD_STATUS_L2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr131170xBCR0x00fff000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L2_REGSilicon Debug Status(Layer2).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTX_TLP_SEQ_NOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_SETDWC_pcie_wire_cpcie_usp_4x8.csr13055Tx Tlp Sequence Number.Indicates next transmit sequence number for transmit TLP.Note: This register field is sticky.1100x000RRX_ACK_SEQ_NOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_SETDWC_pcie_wire_cpcie_usp_4x8.csr13069Tx Ack Sequence Number.Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP.Note: This register field is sticky.23120xfffRDLCMSMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_SETDWC_pcie_wire_cpcie_usp_4x8.csr13084DLCMSM.Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVENote: This register field is sticky.25240x0RFC_INIT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr13097FC_INIT1.Indicates the controller is in FC_INIT1(VC0) state.Note: This register field is sticky.26260x0RFC_INIT2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_SETDWC_pcie_wire_cpcie_usp_4x8.csr13109FC_INIT2.Indicates the controller is in FC_INIT2(VC0) state.Note: This register field is sticky.27270x0RRSVDP_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_SETDWC_pcie_wire_cpcie_usp_4x8.csr13116Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGSD_STATUS_L3FC_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr132410xC0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REGSilicon Debug Status(Layer3 FC).The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE - CREDIT_SEL_HDFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseCREDIT_SEL_VCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_SETDWC_pcie_wire_cpcie_usp_4x8.csr13148Credit Select(VC).This field in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 - 0x1: VC1 - 0x2: VC2 - .. - 0x7: VC7Note: This register field is sticky.200x0R/WCREDIT_SEL_CREDIT_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr13164Credit Select(Credit Type).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Rx - 0x1: TxNote: This register field is sticky.330x0R/WCREDIT_SEL_TLP_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr13181Credit Select(TLP Type).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Posted - 0x1: Non-Posted - 0x2: CompletionNote: This register field is sticky.540x0R/WCREDIT_SEL_HDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_SETDWC_pcie_wire_cpcie_usp_4x8.csr13197Credit Select(HeaderData).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Header Credit - 0x1: Data CreditNote: This register field is sticky.660x0R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr13205Reserved for future use.770x0RCREDIT_DATA0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_SETDWC_pcie_wire_cpcie_usp_4x8.csr13222Credit Data0.Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed ValueNote: This register field is sticky.1980x000RCREDIT_DATA1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_SETDWC_pcie_wire_cpcie_usp_4x8.csr13240Credit Data1.Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when DLCMSM=0x3(DL_ACTIVE).Note: This register field is sticky.31200x000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGSD_STATUS_L3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr132970xC4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L3_REGSilicon Debug Status(Layer3).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseMFTLP_POINTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr13277First Malformed TLP Error Pointer.Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length miss match - 05h: Max payload size - 06h: Message TLP without TC0 - 07h: Invalid TC - 08h: Unexpected route bit in Message TLP - 09h: Unexpected CRS status in Completion TLP - 0Ah: Byte enable - 0Bh: Memory Address 4KB boundary - 0Ch: TLP prefix rules - 0Dh: Translation request rules - 0Eh: Invalid TLP type - 0Fh: Completion rules - 7Fh: Application - Else: ReservedNote: This register field is sticky.600x00RMFTLP_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr13288Malformed TLP Status.Indicates malformed TLP has occurred.770x0R/W1CRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr13296Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGSD_EQ_CONTROL1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr134370xD0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REGSilicon Debug EQ Control 1.This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport registers.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_LANE_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr13325EQ Status Lane Select.Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.300x0R/WEQ_RATE_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr13342EQ Status Rate Select.Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed (include ESM data rate) - 0x1: 16.0GT/s Speed (include ESM data rate) - 0x2: 32.0GT/s SpeedNote: This register field is sticky.540x0R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr13350Reserved for future use.760x0REXT_EQ_TIMEOUTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_SETDWC_pcie_wire_cpcie_usp_4x8.csr13374Extends EQ Phase2/3 Timeout.This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set, the value of EQ2/3 timeout is extended.EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10: 240ms (x10) - 11: No timeoutEQ Slave(DSP in EQ Phase2/USP in EQ Phase3). - 00: 32ms (default) - 01: 56ms (32ms+24ms) - 10: 248ms (32ms +9*24ms) - 11: No timeoutNote: This register field is sticky.980x0R/WRSVDP_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_SETDWC_pcie_wire_cpcie_usp_4x8.csr13382Reserved for future use.15100x00REVAL_INTERVAL_TIMEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_SETDWC_pcie_wire_cpcie_usp_4x8.csr13400Eval Interval Time.Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4usThis field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2).Note: This register field is sticky.17160x0R/WRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr13408Reserved for future use.22180x00RFOM_TARGET_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr13420FOM Target Enable.Enables the FOM_TARGET fields.Note: This register field is sticky.23230x0R/WFOM_TARGETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_SETDWC_pcie_wire_cpcie_usp_4x8.csr13436FOM Target.Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2).This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit).Note: This register field is sticky.31240x00R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGSD_EQ_CONTROL2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr135810xD4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REGSilicon Debug EQ Control 2.This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_LOCAL_TX_PRE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr13459Force Local Transmitter Pre-cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.500x00R/WFORCE_LOCAL_TX_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr13473Force Local Transmitter Cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.1160x00R/WFORCE_LOCAL_TX_POST_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr13487Force Local Transmitter Post-Cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.17120x00R/WFORCE_LOCAL_RX_HINTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_SETDWC_pcie_wire_cpcie_usp_4x8.csr13504Force Local Receiver Preset Hint.Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.20180x0R/WRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_SETDWC_pcie_wire_cpcie_usp_4x8.csr13512Reserved for future use.23210x0RFORCE_LOCAL_TX_PRESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_SETDWC_pcie_wire_cpcie_usp_4x8.csr13528Force Local Transmitter Preset.Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.Note: This register field is sticky.27240x0R/WFORCE_LOCAL_TX_COEF_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr13542Force Local Transmitter Coefficient Enable.Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSORNote: This register field is sticky.28280x0R/WFORCE_LOCAL_RX_HINT_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr13557Force Local Receiver Preset Hint Enable.Enables the FORCE_LOCAL_RX_HINT field.If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.29290x0R/WFORCE_LOCAL_TX_PRESET_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr13572Force Local Transmitter Preset Enable.Enables the FORCE_LOCAL_TX_PRESET field.If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr13580Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGSD_EQ_CONTROL3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr136650xD8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REGSilicon Debug EQ Control 3.This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_REMOTE_TX_PRE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr13603Force Remote Transmitter Pre-Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.500x00R/WFORCE_REMOTE_TX_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr13617Force Remote Transmitter Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.1160x00R/WFORCE_REMOTE_TX_POST_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr13631Force Remote Transmitter Post-Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.17120x00R/WRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr13639Reserved for future use.27180x000RFORCE_REMOTE_TX_COEF_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr13656Force Remote Transmitter Coefficient Enable.Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSORThis function can only be used when GEN3_EQ_FB_MODE = 0000b(Direction Change)Note: This register field is sticky.28280x0R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr13664Reserved for future use.31290x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGSD_EQ_STATUS1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr138090xE0R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REGSilicon Debug EQ Status 1.This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.The following fields are available when Equalization finished unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_VIOLATION - EQ_REJECT_EVENTFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_SEQUENCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr13695EQ Sequence.Indicates that the controller is starting the equalization sequence.Note: This register field is sticky.000x0REQ_CONVERGENCE_INFOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_SETDWC_pcie_wire_cpcie_usp_4x8.csr13714EQ Convergence Info.Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: ReservedThis bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.210x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr13721Reserved for future use.330x0REQ_RULEA_VIOLATIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_SETDWC_pcie_wire_cpcie_usp_4x8.csr13742EQ Rule A Violation.Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to the rules a) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.440x0REQ_RULEB_VIOLATIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_SETDWC_pcie_wire_cpcie_usp_4x8.csr13763EQ Rule B Violation.Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to the rules b) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.550x0REQ_RULEC_VIOLATIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_SETDWC_pcie_wire_cpcie_usp_4x8.csr13784EQ Rule C Violation.Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to the rules c) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.660x0REQ_REJECT_EVENTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_SETDWC_pcie_wire_cpcie_usp_4x8.csr13801EQ Reject Event.Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2).This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.770x0RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr13808Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGSD_EQ_STATUS2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr138970xE4R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REGSilicon Debug EQ Status 2.This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_LOCAL_PRE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr13834EQ Local Pre-Cursor.Indicates Local pre cursor coefficient value.Note: This register field is sticky.500x00REQ_LOCAL_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr13847EQ Local Cursor.Indicates Local cursor coefficient value.Note: This register field is sticky.1160x00REQ_LOCAL_POST_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr13860EQ Local Post-Cursor.Indicates Local post cursor coefficient value.Note: This register field is sticky.17120x00REQ_LOCAL_RX_HINTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_SETDWC_pcie_wire_cpcie_usp_4x8.csr13876EQ Local Receiver Preset Hint.Indicates Local Receiver Preset Hint value.If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.20180x0RRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_SETDWC_pcie_wire_cpcie_usp_4x8.csr13883Reserved for future use.23210x0REQ_LOCAL_FOM_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr13896EQ Local Figure of Merit.Indicates Local maximum Figure of Merit value.Note: This register field is sticky.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGSD_EQ_STATUS3_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr139820xE8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REGSilicon Debug EQ Status 3.This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_REMOTE_PRE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr13922EQ Remote Pre-Cursor.Indicates Remote pre cursor coefficient value.Note: This register field is sticky.500x00REQ_REMOTE_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr13935EQ Remote Cursor.Indicates Remote cursor coefficient value.Note: This register field is sticky.1160x00REQ_REMOTE_POST_CURSORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr13948EQ Remote Post-Cursor.Indicates Remote post cursor coefficient value.Note: This register field is sticky.17120x00REQ_REMOTE_LFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_SETDWC_pcie_wire_cpcie_usp_4x8.csr13961EQ Remote LF.Indicates Remote LF value.Note: This register field is sticky.23180x00REQ_REMOTE_FSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_SETDWC_pcie_wire_cpcie_usp_4x8.csr13974EQ Remote FS.Indicates Remote FS value.Note: This register field is sticky.29240x00RRSVDP_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_SETDWC_pcie_wire_cpcie_usp_4x8.csr13981Reserved for future use.31300x0RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAPPF0_VSECRAS_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr150360x3C4R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAPPF RAS Datapath Protection Capability Structure (VSEC)registerPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFRASDP_EXT_CAP_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr140430x0R0x3fc1000bPE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFFPCIe Extended capability ID, Capability version and Next capability offset.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr14010PCI Express Extended Capability ID.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x000bRCAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr14026Capability Version.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr14042Next Capability Offset.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x3fcRregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFRASDP_VENDOR_SPECIFIC_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr140860x4R0x03810001PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFFVendor Specific Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVSEC_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr14061VSEC ID.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1500x0001RVSEC_REVPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_SETDWC_pcie_wire_cpcie_usp_4x8.csr14073VSEC Rev.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.19160x1RVSEC_LENGTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr14085VSEC Length.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.31200x038RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFRASDP_ERROR_PROT_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr14292ECC error correction control0x8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFFECC error correction control. Allows you to disable ECC error correction for RAMs and datapath.When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock (core_clk), you must not write this register while operations are in progress in the AXI master / slave interface.falsefalsefalsefalseERROR_PROT_DISABLE_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_SETDWC_pcie_wire_cpcie_usp_4x8.csr14110Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.Note: This register field is sticky.000x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_MASTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr14121Error correction disable for AXI bridge master completion buffer.Note: This register field is sticky.110x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUNDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_SETDWC_pcie_wire_cpcie_usp_4x8.csr14132Error correction disable for AXI bridge outbound request path.Note: This register field is sticky.220x0R/WERROR_PROT_DISABLE_DMA_WRITEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_SETDWC_pcie_wire_cpcie_usp_4x8.csr14142Error correction disable for DMA write engine.Note: This register field is sticky.330x0R/WERROR_PROT_DISABLE_LAYER2_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_SETDWC_pcie_wire_cpcie_usp_4x8.csr14152Error correction disable for layer 2 Tx path.Note: This register field is sticky.440x0R/WERROR_PROT_DISABLE_LAYER3_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_SETDWC_pcie_wire_cpcie_usp_4x8.csr14162Error correction disable for layer 3 Tx path.Note: This register field is sticky.550x0R/WERROR_PROT_DISABLE_ADM_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_SETDWC_pcie_wire_cpcie_usp_4x8.csr14172Error correction disable for Adm Tx path.Note: This register field is sticky.660x0R/WERROR_PROT_DISABLE_CXS_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_SETDWC_pcie_wire_cpcie_usp_4x8.csr14182Error correction disable for CXS Rx path (PCIe Tx path).Note: This register field is sticky.770x0R/WERROR_PROT_DISABLE_DTIM_TXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_SETDWC_pcie_wire_cpcie_usp_4x8.csr14192Error correction disable for DTIM Tx path.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr14200Reserved for future use.1590x00RERROR_PROT_DISABLE_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_SETDWC_pcie_wire_cpcie_usp_4x8.csr14210Global error correction disable for all Rx layers.Note: This register field is sticky.16160x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_SETDWC_pcie_wire_cpcie_usp_4x8.csr14222Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.Note: This register field is sticky.17170x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUESTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_SETDWC_pcie_wire_cpcie_usp_4x8.csr14233Error correction disable for AXI bridge inbound request path.Note: This register field is sticky.18180x0R/WERROR_PROT_DISABLE_DMA_READPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_SETDWC_pcie_wire_cpcie_usp_4x8.csr14243Error correction disable for DMA read engine.Note: This register field is sticky.19190x0R/WERROR_PROT_DISABLE_LAYER2_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_SETDWC_pcie_wire_cpcie_usp_4x8.csr14253Error correction disable for layer 2 Rx path.Note: This register field is sticky.20200x0R/WERROR_PROT_DISABLE_LAYER3_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_SETDWC_pcie_wire_cpcie_usp_4x8.csr14263Error correction disable for layer 3 Rx path.Note: This register field is sticky.21210x0R/WERROR_PROT_DISABLE_ADM_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_SETDWC_pcie_wire_cpcie_usp_4x8.csr14273Error correction disable for ADM Rx path.Note: This register field is sticky.22220x0R/WERROR_PROT_DISABLE_CXS_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_SETDWC_pcie_wire_cpcie_usp_4x8.csr14283Error correction disable for CXS Tx path (PCIe Rx path).Note: This register field is sticky.23230x0R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr14291Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFRASDP_CORR_COUNTER_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr143790xCR/W0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFFCorrected error (1-bit ECC) counter selection and control.This is a viewport control register.Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_CORR_COUNT_REPORT_OFF viewport data register.falsefalsefalsefalseCORR_CLEAR_COUNTERSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_SETDWC_pcie_wire_cpcie_usp_4x8.csr14309Clear all correctable error counters.000x0WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr14317Reserved for future use.310x0RCORR_EN_COUNTERSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_SETDWC_pcie_wire_cpcie_usp_4x8.csr14329Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozenThe counters are enabled by default.440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr14337Reserved for future use.1950x0000RCORR_COUNTER_SELECTION_REGIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_SETDWC_pcie_wire_cpcie_usp_4x8.csr14363Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0R/WCORR_COUNTER_SELECTIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_SETDWC_pcie_wire_cpcie_usp_4x8.csr14378Counter selection.This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFRASDP_CORR_COUNT_REPORT_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr144410x10R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFFCorrected error (1-bit ECC) counter data.This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register.falsefalsefalsefalseCORR_COUNTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr14395Current corrected error count for the selected counter.700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr14402Reserved for future use.1980x000RCORR_COUNTER_SELECTED_REGIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_SETDWC_pcie_wire_cpcie_usp_4x8.csr14429Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0RCORR_COUNTER_SELECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr14440Counter selection.Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFRASDP_UNCORR_COUNTER_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr145320x14R/W0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFFUncorrected error (2-bit ECC and parity) counter selection and control.This is a viewport control register.Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_UNCORR_COUNT_REPORT_OFF viewport data register.falsefalsefalsefalseUNCORR_CLEAR_COUNTERSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_SETDWC_pcie_wire_cpcie_usp_4x8.csr14461Clear uncorrectable errors counters.When asserted causes all counters tracking the uncorrectable errors to be cleared.000x0WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr14469Reserved for future use.310x0RUNCORR_EN_COUNTERSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_SETDWC_pcie_wire_cpcie_usp_4x8.csr14481Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozenThe counters are enabled by default.440x1R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr14489Reserved for future use.1950x0000RUNCORR_COUNTER_SELECTION_REGIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_SETDWC_pcie_wire_cpcie_usp_4x8.csr14515Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0R/WUNCORR_COUNTER_SELECTIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_SETDWC_pcie_wire_cpcie_usp_4x8.csr14531Counter selection.This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFRASDP_UNCORR_COUNT_REPORT_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr145950x18R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFFUncorrected error (2-bit ECC and parity) counter data.This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF register.falsefalsefalsefalseUNCORR_COUNTERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr14549Current uncorrected error count for the selected counter700x00RRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr14556Reserved for future use.1980x000RUNCORR_COUNTER_SELECTED_REGIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_SETDWC_pcie_wire_cpcie_usp_4x8.csr14583Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0RUNCORR_COUNTER_SELECTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr14594Counter selection.Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFRASDP_ERROR_INJ_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr14675Error injection control0x1CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFFError injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occursfalsefalsefalsefalseERROR_INJ_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr14613Error injection global enable.When set enables the error insertion logic.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr14621Reserved for future use.310x0RERROR_INJ_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr14632Error injection type: - 0: none - 1: 1-bit - 2: 2-bit540x0R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr14640Reserved for future use.760x0RERROR_INJ_COUNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr14653Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected1580x00R/WERROR_INJ_LOCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_SETDWC_pcie_wire_cpcie_usp_4x8.csr14666Error injection location.Selects where error injection takes place.You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf23160x00R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr14674Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFRASDP_CORR_ERROR_LOCATION_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr14782Corrected errors locations.0x20R0x00d000d0PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFFCorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr14690Reserved for future use.300x0RREG_FIRST_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr14717Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved740xdRLOC_FIRST_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr14732Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf1580x00RRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr14739Reserved for future use.19160x0RREG_LAST_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr14766Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200xdRLOC_LAST_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr14781Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFRASDP_UNCORR_ERROR_LOCATION_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr14889Uncorrected errors locations.0x24R0x00d000d0PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFFUncorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr14797Reserved for future use.300x0RREG_FIRST_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr14824Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved740xdRLOC_FIRST_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr14839Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf1580x00RRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr14846Reserved for future use.19160x0RREG_LAST_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr14873Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200xdRLOC_LAST_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr14888Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFRASDP_ERROR_MODE_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr14933RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error.0x28R/W0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFFRASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be correct; you must discard them.For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_MODE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr14913Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error.Note: This register field is sticky.000x1R/WAUTO_LINK_DOWN_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr14924Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode.Note: This register field is sticky.110x0R/WRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr14932Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFRASDP_ERROR_MODE_CLEAR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr14961Exit RASDP error mode.0x2CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFFExit RASDP error mode. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_MODE_CLEARPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_SETDWC_pcie_wire_cpcie_usp_4x8.csr14952Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs.000x0WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr14960Reserved for future use.3110x00000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFRASDP_RAM_ADDR_CORR_ERROR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr14998RAM Address where a corrected error (1-bit ECC) has been detected.0x30R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFFRAM Address where a corrected error (1-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRAM_ADDR_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr14980RAM Address where a corrected error (1-bit ECC) has been detected.2600x0000000RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr14987Reserved for future use.27270x0RRAM_INDEX_CORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr14997RAM index where a corrected error (1-bit ECC) has been detected.31280x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFRASDP_RAM_ADDR_UNCORR_ERROR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr15035RAM Address where an uncorrected error (2-bit ECC) has been detected.0x34R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFFRAM Address where an uncorrected error (2-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRAM_ADDR_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr15017RAM Address where an uncorrected error (2-bit ECC) has been detected.2600x0000000RRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr15024Reserved for future use.27270x0RRAM_INDEX_UNCORR_ERRORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr15034RAM index where an uncorrected error (2-bit ECC) has been detected.31280x0RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAPPF0_DLINK_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr152160x3FCRPE0_DWC_pcie_ctl_AXI_Slave_PF0_DLINK_CAPPF DLINK Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFDATA_LINK_FEATURE_EXT_HDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr15110This register provides capbility ID, capability version and next offset value.0x0R0x40810025PE0_DWC_pcie_ctl_AXI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFFData Link Feature Extended Capability Header.This register provides capbility ID, capability version and next offset value.falsefalsefalsefalseDLINK_EXT_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr15066Capability ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.Extended Capability ID for Data Link Feature is 0025h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0025RDLINK_CAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr15083Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RDLINK_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr15109Next Capability Offset.This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities.For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x408RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFDATA_LINK_FEATURE_CAP_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr15171This register provides description about extended feature.0x4R0x80000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFFData Link Feature Capabilities.This register provides description about extended feature.falsefalsefalsefalseSCALED_FLOW_CNTL_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr15134Local Scaled Flow Control Supported.Bit 0 – Local Scaled Flow Control Supported. Bit 22:1 – RsvdP.Bits associated with features that this Port is capable of supporting are HwInit, defaulting to 1b.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 000x1RFUTURE_FEATURE_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr15148Local Future Data Link Feature Supported.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.2210x000000RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr15155Reserved for future use.30230x00RDL_FEATURE_EXCHANGE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr15170Data Link Feature Exchange Enable.If Set, this bit indicates that this Port will enter the DL_Feature negotiation state. Default is 1b.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 31310x1RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFDATA_LINK_FEATURE_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr15215This Registor privides status of the capability of data link feature.0x8R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFFData Link Feature Status Register.This Registor privides status of the capability of data link feature.falsefalsefalsefalseREMOTE_DATA_LINK_FEATURE_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr15192Remote Data Link Feature SupportedFeatures Currently defined are: Bit 0 - Remote Scaled Flow Control Supported.Other Bits are undefined. Default value is 00 0000h.2200x000000RRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr15199Reserved for future use.30230x00RDATA_LINK_FEATURE_STATUS_VALIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_SETDWC_pcie_wire_cpcie_usp_4x8.csr15214Remote Data Link Feature Supported Valid.This bit indicates that the Port has received a Data Link Feature DLLP in state DL_Feature (see Section 3.2.1) and that the Remote Data Link Feature Supported and Remote Data Link Feature Ack fields arefield is meaningful. This bit is Cleared on entry to state DL_Inactive.Default is 0b.31310x0RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAPPF0_RESBAR_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr161180x408R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_RESBAR_CAPResizable BAR Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REGRESBAR_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr152750x0R0x44810015PE0_DWC_pcie_ctl_AXI_Slave_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REGResizable BAR Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRESBAR_EXT_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr15242Resizable BAR Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0015RRESBAR_CAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr15258Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RRESBAR_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr15274Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x448RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REGRESBAR_CAP_REG_0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr157650x4R0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REGResizable BAR0 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr15288Reserved for future use.300x0RRESBAR_CAP_REG_0_1MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15305Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1RRESBAR_CAP_REG_0_2MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15322Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0RRESBAR_CAP_REG_0_4MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15339Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0RRESBAR_CAP_REG_0_8MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15356Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0RRESBAR_CAP_REG_0_16MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15373Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RRESBAR_CAP_REG_0_32MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15390Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RRESBAR_CAP_REG_0_64MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15407Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RRESBAR_CAP_REG_0_128MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15424Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0RRESBAR_CAP_REG_0_256MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15441Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0RRESBAR_CAP_REG_0_512MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15458Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0RRESBAR_CAP_REG_0_1GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15475Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0RRESBAR_CAP_REG_0_2GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15492Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0RRESBAR_CAP_REG_0_4GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15509Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RRESBAR_CAP_REG_0_8GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15526Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RRESBAR_CAP_REG_0_16GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15543Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RRESBAR_CAP_REG_0_32GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15560Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RRESBAR_CAP_REG_0_64GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15577Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RRESBAR_CAP_REG_0_128GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15594Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RRESBAR_CAP_REG_0_256GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15611Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RRESBAR_CAP_REG_0_512GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15628Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RRESBAR_CAP_REG_0_1TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15645Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RRESBAR_CAP_REG_0_2TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15662Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RRESBAR_CAP_REG_0_4TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15679Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RRESBAR_CAP_REG_0_8TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15696Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RRESBAR_CAP_REG_0_16TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15713Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RRESBAR_CAP_REG_0_32TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15730Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RRESBAR_CAP_REG_0_64TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15747Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RRESBAR_CAP_REG_0_128TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15764Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REGRESBAR_CTRL_REG_0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr161170x8R/W0x00000020PE0_DWC_pcie_ctl_AXI_Slave_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REGResizable BAR0 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRESBAR_CTRL_REG_IDX_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr15784BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr15792Reserved for future use.430x0RRESBAR_CTRL_REG_NUM_BARSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_wire_cpcie_usp_4x8.csr15806Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x1RRESBAR_CTRL_REG_BAR_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr15820BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr15828Reserved for future use.15140x0RRESBAR_CTRL_REG_0_256TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15846Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RRESBAR_CTRL_REG_0_512TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15864Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RRESBAR_CTRL_REG_0_1PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15882Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RRESBAR_CTRL_REG_0_2PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15900Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RRESBAR_CTRL_REG_0_4PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15918Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RRESBAR_CTRL_REG_0_8PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15936Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RRESBAR_CTRL_REG_0_16PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15954Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RRESBAR_CTRL_REG_0_32PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15972Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RRESBAR_CTRL_REG_0_64PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr15990Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RRESBAR_CTRL_REG_0_128PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16008Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RRESBAR_CTRL_REG_0_256PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16026Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RRESBAR_CTRL_REG_0_512PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16044Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RRESBAR_CTRL_REG_0_1EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16062Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RRESBAR_CTRL_REG_0_2EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16080Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RRESBAR_CTRL_REG_0_4EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16098Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RRESBAR_CTRL_REG_0_8EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16116Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAPPF0_VF_RESBAR_CAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr187040x448R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAPVF Resizable BAR Capability StructureregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REGregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REGVF_RESBAR_CAP_HDR_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr161770x0R0x00010024PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REGResizable BAR Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_EXT_CAP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr16144Resizable BAR Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0024RVF_RESBAR_CAP_VERSIONPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr16160Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RVF_RESBAR_CAP_NEXT_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr16176Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REGVF_RESBAR_CAP_REG_0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr166670x4R0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REGResizable BAR0 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr16190Reserved for future use.300x0RVF_RESBAR_CAP_REG_0_1MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16207Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1RVF_RESBAR_CAP_REG_0_2MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16224Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0RVF_RESBAR_CAP_REG_0_4MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16241Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0RVF_RESBAR_CAP_REG_0_8MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16258Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0RVF_RESBAR_CAP_REG_0_16MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16275Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RVF_RESBAR_CAP_REG_0_32MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16292Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RVF_RESBAR_CAP_REG_0_64MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16309Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RVF_RESBAR_CAP_REG_0_128MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16326Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0RVF_RESBAR_CAP_REG_0_256MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16343Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0RVF_RESBAR_CAP_REG_0_512MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16360Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0RVF_RESBAR_CAP_REG_0_1GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16377Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0RVF_RESBAR_CAP_REG_0_2GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16394Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0RVF_RESBAR_CAP_REG_0_4GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16411Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RVF_RESBAR_CAP_REG_0_8GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16428Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RVF_RESBAR_CAP_REG_0_16GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16445Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RVF_RESBAR_CAP_REG_0_32GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16462Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RVF_RESBAR_CAP_REG_0_64GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16479Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RVF_RESBAR_CAP_REG_0_128GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16496Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RVF_RESBAR_CAP_REG_0_256GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16513Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RVF_RESBAR_CAP_REG_0_512GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16530Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RVF_RESBAR_CAP_REG_0_1TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16547Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RVF_RESBAR_CAP_REG_0_2TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16564Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RVF_RESBAR_CAP_REG_0_4TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16581Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RVF_RESBAR_CAP_REG_0_8TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16598Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RVF_RESBAR_CAP_REG_0_16TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16615Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RVF_RESBAR_CAP_REG_0_32TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16632Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RVF_RESBAR_CAP_REG_0_64TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16649Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RVF_RESBAR_CAP_REG_0_128TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16666Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REGVF_RESBAR_CTRL_REG_0_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr170190x8R/W0x00000060PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REGResizable BAR0 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_CTRL_REG_IDX_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr16686BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr16694Reserved for future use.430x0RVF_RESBAR_CTRL_REG_NUM_BARSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_wire_cpcie_usp_4x8.csr16708Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x3RVF_RESBAR_CTRL_REG_BAR_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr16722BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr16730Reserved for future use.15140x0RVF_RESBAR_CTRL_REG_0_256TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16748Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RVF_RESBAR_CTRL_REG_0_512TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16766Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RVF_RESBAR_CTRL_REG_0_1PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16784Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RVF_RESBAR_CTRL_REG_0_2PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16802Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RVF_RESBAR_CTRL_REG_0_4PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16820Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RVF_RESBAR_CTRL_REG_0_8PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16838Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RVF_RESBAR_CTRL_REG_0_16PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16856Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RVF_RESBAR_CTRL_REG_0_32PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16874Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RVF_RESBAR_CTRL_REG_0_64PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16892Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RVF_RESBAR_CTRL_REG_0_128PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16910Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RVF_RESBAR_CTRL_REG_0_256PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16928Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RVF_RESBAR_CTRL_REG_0_512PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16946Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RVF_RESBAR_CTRL_REG_0_1EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16964Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RVF_RESBAR_CTRL_REG_0_2EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr16982Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RVF_RESBAR_CTRL_REG_0_4EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17000Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RVF_RESBAR_CTRL_REG_0_8EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17018Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REGVF_RESBAR_CAP_REG_1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr175090xCR0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REGResizable BAR1 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr17032Reserved for future use.300x0RVF_RESBAR_CAP_REG_1_1MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17049Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1RVF_RESBAR_CAP_REG_1_2MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17066Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0RVF_RESBAR_CAP_REG_1_4MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17083Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0RVF_RESBAR_CAP_REG_1_8MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17100Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0RVF_RESBAR_CAP_REG_1_16MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17117Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RVF_RESBAR_CAP_REG_1_32MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17134Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RVF_RESBAR_CAP_REG_1_64MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17151Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RVF_RESBAR_CAP_REG_1_128MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17168Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0RVF_RESBAR_CAP_REG_1_256MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17185Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0RVF_RESBAR_CAP_REG_1_512MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17202Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0RVF_RESBAR_CAP_REG_1_1GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17219Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0RVF_RESBAR_CAP_REG_1_2GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17236Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0RVF_RESBAR_CAP_REG_1_4GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17253Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RVF_RESBAR_CAP_REG_1_8GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17270Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RVF_RESBAR_CAP_REG_1_16GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17287Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RVF_RESBAR_CAP_REG_1_32GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17304Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RVF_RESBAR_CAP_REG_1_64GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17321Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RVF_RESBAR_CAP_REG_1_128GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17338Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RVF_RESBAR_CAP_REG_1_256GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17355Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RVF_RESBAR_CAP_REG_1_512GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17372Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RVF_RESBAR_CAP_REG_1_1TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17389Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RVF_RESBAR_CAP_REG_1_2TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17406Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RVF_RESBAR_CAP_REG_1_4TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17423Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RVF_RESBAR_CAP_REG_1_8TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17440Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RVF_RESBAR_CAP_REG_1_16TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17457Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RVF_RESBAR_CAP_REG_1_32TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17474Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RVF_RESBAR_CAP_REG_1_64TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17491Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RVF_RESBAR_CAP_REG_1_128TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17508Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REGVF_RESBAR_CTRL_REG_1_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr178610x10R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REGResizable BAR1 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_CTRL_REG_IDX_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr17528BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr17536Reserved for future use.430x0RVF_RESBAR_CTRL_REG_NUM_BARSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_wire_cpcie_usp_4x8.csr17550Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x0RVF_RESBAR_CTRL_REG_BAR_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr17564BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr17572Reserved for future use.15140x0RVF_RESBAR_CTRL_REG_1_256TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17590Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RVF_RESBAR_CTRL_REG_1_512TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17608Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RVF_RESBAR_CTRL_REG_1_1PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17626Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RVF_RESBAR_CTRL_REG_1_2PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17644Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RVF_RESBAR_CTRL_REG_1_4PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17662Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RVF_RESBAR_CTRL_REG_1_8PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17680Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RVF_RESBAR_CTRL_REG_1_16PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17698Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RVF_RESBAR_CTRL_REG_1_32PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17716Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RVF_RESBAR_CTRL_REG_1_64PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17734Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RVF_RESBAR_CTRL_REG_1_128PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17752Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RVF_RESBAR_CTRL_REG_1_256PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17770Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RVF_RESBAR_CTRL_REG_1_512PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17788Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RVF_RESBAR_CTRL_REG_1_1EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17806Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RVF_RESBAR_CTRL_REG_1_2EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17824Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RVF_RESBAR_CTRL_REG_1_4EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17842Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RVF_RESBAR_CTRL_REG_1_8EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17860Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REGVF_RESBAR_CAP_REG_2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr183510x14R0x00000010PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REGResizable BAR2 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr17874Reserved for future use.300x0RVF_RESBAR_CAP_REG_2_1MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17891Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1RVF_RESBAR_CAP_REG_2_2MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17908Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0RVF_RESBAR_CAP_REG_2_4MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17925Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0RVF_RESBAR_CAP_REG_2_8MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17942Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0RVF_RESBAR_CAP_REG_2_16MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17959Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RVF_RESBAR_CAP_REG_2_32MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17976Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RVF_RESBAR_CAP_REG_2_64MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr17993Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RVF_RESBAR_CAP_REG_2_128MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18010Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0RVF_RESBAR_CAP_REG_2_256MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18027Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0RVF_RESBAR_CAP_REG_2_512MBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18044Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0RVF_RESBAR_CAP_REG_2_1GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18061Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0RVF_RESBAR_CAP_REG_2_2GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18078Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0RVF_RESBAR_CAP_REG_2_4GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18095Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RVF_RESBAR_CAP_REG_2_8GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18112Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RVF_RESBAR_CAP_REG_2_16GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18129Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RVF_RESBAR_CAP_REG_2_32GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18146Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RVF_RESBAR_CAP_REG_2_64GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18163Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RVF_RESBAR_CAP_REG_2_128GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18180Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RVF_RESBAR_CAP_REG_2_256GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18197Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RVF_RESBAR_CAP_REG_2_512GBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18214Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RVF_RESBAR_CAP_REG_2_1TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18231Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RVF_RESBAR_CAP_REG_2_2TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18248Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RVF_RESBAR_CAP_REG_2_4TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18265Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RVF_RESBAR_CAP_REG_2_8TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18282Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RVF_RESBAR_CAP_REG_2_16TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18299Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RVF_RESBAR_CAP_REG_2_32TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18316Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RVF_RESBAR_CAP_REG_2_64TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18333Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RVF_RESBAR_CAP_REG_2_128TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18350Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REGVF_RESBAR_CTRL_REG_2_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr187030x18R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REGResizable BAR2 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_CTRL_REG_IDX_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr18370BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr18378Reserved for future use.430x0RVF_RESBAR_CTRL_REG_NUM_BARSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_wire_cpcie_usp_4x8.csr18392Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x0RVF_RESBAR_CTRL_REG_BAR_SIZEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr18406BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr18414Reserved for future use.15140x0RVF_RESBAR_CTRL_REG_2_256TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18432Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RVF_RESBAR_CTRL_REG_2_512TBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18450Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RVF_RESBAR_CTRL_REG_2_1PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18468Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RVF_RESBAR_CTRL_REG_2_2PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18486Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RVF_RESBAR_CTRL_REG_2_4PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18504Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RVF_RESBAR_CTRL_REG_2_8PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18522Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RVF_RESBAR_CTRL_REG_2_16PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18540Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RVF_RESBAR_CTRL_REG_2_32PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18558Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RVF_RESBAR_CTRL_REG_2_64PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18576Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RVF_RESBAR_CTRL_REG_2_128PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18594Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RVF_RESBAR_CTRL_REG_2_256PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18612Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RVF_RESBAR_CTRL_REG_2_512PBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18630Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RVF_RESBAR_CTRL_REG_2_1EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18648Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RVF_RESBAR_CTRL_REG_2_2EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18666Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RVF_RESBAR_CTRL_REG_2_4EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18684Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RVF_RESBAR_CTRL_REG_2_8EBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr18702Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RgroupPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGICPF0_PORT_LOGICPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr245460x700R/WPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGICPort LogicregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFACK_LATENCY_TIMER_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr187610x0R/W0x0c23040bPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFFAck Latency Timer and Replay Timer Register.falsefalsefalsefalseROUND_TRIP_LATENCY_TIME_LIMITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr18736Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details, see "Ack Scheduling".You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed.The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 3.0 specification.The limit must reflect the round trip latency from requester to completer.If there is a change in the payload size or link width, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.1500x040bR/WREPLAY_TIME_LIMITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr18760Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details, see "Transmit Replay".You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed.The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 3.0 specification.If there is a change in the payload size or link speed, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.31160x0c23R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFVENDOR_SPEC_DLLP_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr187830x4R/W0xffffffffPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFFVendor Specific DLLP Register.falsefalsefalsefalseVENDOR_SPEC_DLLPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SETDWC_pcie_wire_cpcie_usp_4x8.csr18782Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP.Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register, then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to send the DLLP. - [7:0] = Type - [31:8] = Payload (24 bits)The dllp type is in bits [7:0] while the remainder is the vendor defined payload.Note: This register field is sticky.3100xffffffffR/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFPORT_FORCE_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr188770x8R/W0x00800004PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PORT_FORCE_OFFPort Force Link Register.falsefalsefalsefalseLINK_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_SETDWC_pcie_wire_cpcie_usp_4x8.csr18795Link Number. Not used for endpoint. Not used for M-PCIe.Note: This register field is sticky.700x04R/WFORCED_LTSSMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_SETDWC_pcie_wire_cpcie_usp_4x8.csr18808Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link).Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v.Note: This register field is sticky.1180x0R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr18816Reserved for future use.14120x0RFORCE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr18835Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state, and to force the controller to transmit a specific Link Command. Asserting this bit triggers the following actions: - Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the controller to transmit the command specified by the Forced Link Command field.This is a self-clearing register field. Reading from this register field always returns a "0".15150x0WLINK_STATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_SETDWC_pcie_wire_cpcie_usp_4x8.csr18847Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link).LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v.Note: This register field is sticky.21160x00R/WRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr18855Reserved for future use.22220x0RDO_DESKEW_FOR_SRISPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SETDWC_pcie_wire_cpcie_usp_4x8.csr18868Use the transitions from TS2 to Logical Idle Symbol, SKP OS to Logical Idle Symbol, EIEOS to Logical Idle Symbol, and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS is set to 1.Note: This register field is sticky.23230x1R/WRSVDP_24PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr18876Reserved for future use.31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFACK_F_ASPM_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr190040xCR/W0x1bc8c800PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFFAck Frequency and L0-L1 ASPM Control Register.falsefalsefalsefalseACK_FREQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr18905Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK request for every TLP that it receives. The controller waits until the ACK Latency Timer expires, then converts the current low-priority ACK request to a high-priority ACK request and schedules the DLLP for transmission to the remote link partner. - 1-255: Indicates that the controller will schedule a high-priority ACK after receiving this number of TLPs. It might schedule the ACK before receiving this number of TLPs if the ACK Latency Timer expires, but never later.For a typical system, you do not have to modify the default setting. For more details, see "ACK/NAK Scheduling".Note: This register field is sticky.700x00R/WACK_N_FTSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SETDWC_pcie_wire_cpcie_usp_4x8.csr18921N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255.The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.1580xc8R/WCOMMON_CLK_N_FTSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SETDWC_pcie_wire_cpcie_usp_4x8.csr18947Common Clock N_FTS. This is the N_FTS when common clock is used.The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. This field is only writable (sticky) when all of the following configuration parameter equations are true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYThe controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 23160xc8RL0S_ENTRANCE_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SETDWC_pcie_wire_cpcie_usp_4x8.csr18964L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 usThis field is applicable to STALL while in L0 for M-PCIe.Note: This register field is sticky.26240x3R/WL1_ENTRANCE_LATENCYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SETDWC_pcie_wire_cpcie_usp_4x8.csr18983L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 usNote: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite.Note: This register field is sticky.29270x3R/WENTER_ASPMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SETDWC_pcie_wire_cpcie_usp_4x8.csr18995ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s.Note: This register field is sticky.30300x0R/WRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr19003Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFPORT_LINK_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr192000x10R/W0x00000120PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFFPort Link Control Register.falsefalsefalsefalseVENDOR_SPECIFIC_DLLP_REQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr19021Vendor Specific DLLP Request. When software writes a '1' to this bit, the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF.Reading from this self-clearing register field always returns a '0'.000x0R/W1CSCRAMBLE_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr19030Scramble Disable. Turns off data scrambling.Note: This register field is sticky.110x0R/WLOOPBACK_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr19046Loopback Enable. Turns on loopback. For more details, see "Loopback".For M-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during Configuration.start state(initial discovery/configuration).M-PCIe doesn't support loopback mode from L0 state - only from Configuration.start.Note: This register field is sticky.220x0R/WRESET_ASSERTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_SETDWC_pcie_wire_cpcie_usp_4x8.csr19056Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only).Note: This register field is sticky.330x0R/WRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr19064Reserved for future use.440x0RDLL_LINK_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr19075DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the controller does not transmit InitFC DLLPs and does not establish a link.Note: This register field is sticky.550x1R/WLINK_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr19084LINK_DISABLE is an internally reserved field. Do not use.Note: This register field is sticky.660x0R/WFAST_LINK_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr19111Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster.The default scaling factor can be changed using the DEFAULT_FAST_LINK_SCALING_FACTOR parameter or through the FAST_LINK_SCALING_FACTOR field in the TIMER_CTRL_MAX_FUNC_NUM_OFF register.Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to '1'.For more details, see the "Fast Link Simulation Mode" section in the "Integrating the Controller with the PHY or Application RTL or Verification IP" chapter of the User Guide.For M-PCIe, this field also affects Remain Hibern8 Time, Minimum Activate Time, and RRAP timeout. If this bit is set to '1', tRRAPInitiatorResponse is set to 1.88 ms(60 ms/32).Note: This register field is sticky.770x0R/WLINK_RATEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_SETDWC_pcie_wire_cpcie_usp_4x8.csr19120LINK_RATE is an internally reserved field. Do not use.Note: This register field is sticky.1180x1R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr19128Reserved for future use.15120x0RLINK_CAPABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr19152Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing the link width, see "Link Establishment". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supported)This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.2116R/W--23220x0rBEACON_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr19161BEACON_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.24240x0R/WCORRUPT_LCRC_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr19171CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.25250x0R/WEXTENDED_SYNCHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr19181EXTENDED_SYNCH is an internally reserved field. Do not use.Note: This register field is sticky.26260x0R/WTRANSMIT_LANE_REVERSALE_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr19191TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.27270x0R/WRSVDP_28PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_SETDWC_pcie_wire_cpcie_usp_4x8.csr19199Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFLANE_SKEW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr192810x14R/W0x3c000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_LANE_SKEW_OFFLane Skew Register.falsefalsefalsefalseINSERT_LANE_SKEWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_SETDWC_pcie_wire_cpcie_usp_4x8.csr19213INSERT_LANE_SKEW is an internally reserved field. Do not use.Note: This register field is sticky.2300x000000R/WFLOW_CTRL_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr19223Flow Control Disable. Prevents the controller from sending FC DLLPs.Note: This register field is sticky.24240x0R/WACK_NAK_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr19233Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs.Note: This register field is sticky.25250x0R/WELASTIC_BUFFER_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr19244Selects Elasticity Buffer operating mode:0: Nominal Half Full Buffer mode1: Nominal Empty Buffer ModeNote: This register field is sticky.26260x1R/WIMPLEMENT_NUM_LANESPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_SETDWC_pcie_wire_cpcie_usp_4x8.csr19270Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanesThe number of lanes to be used when in Loopback Master. The number of lanes programmed must be equal to or less than the valid number of lanes set in LINK_CAPABLE field. You must configure this field before initiating Loopback by writing in the LOOPBACK_ENABLE field.The controller will transition from Loopback.Entry to Loopback.Active after receiving two consecutive TS1 Ordered Sets with the Loopback bit asserted on the implementation specific number of lanes configured in this field.Note: This register field is sticky.30270x7R/WDISABLE_LANE_TO_LANE_DESKEWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_SETDWC_pcie_wire_cpcie_usp_4x8.csr19280Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFTIMER_CTRL_MAX_FUNC_NUM_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr193780x18R/W0x40000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFFTimer Control and Max Function Number Register.falsefalsefalsefalseMAX_FUNC_NUMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SETDWC_pcie_wire_cpcie_usp_4x8.csr19295Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request).Note: This register field is sticky.700x00R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr19303Reserved for future use.1380x00RTIMER_MOD_REPLAY_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SETDWC_pcie_wire_cpcie_usp_4x8.csr19323Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed. A value of "0" represents no modification to the timer limit. For more details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.At Gen3 speed, the controller automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ.For M-PCIe, this field increases the time-out value for the replay timer in increments of 64 clock cycles at HS-Gear1, HS-Gear2, or HS-Gear3 speed.Note: This register field is sticky.1814R/WTIMER_MOD_ACK_NAKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SETDWC_pcie_wire_cpcie_usp_4x8.csr19337Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of "0" represents no modification to the timer value. For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.Note: This register field is sticky.23190x00R/WUPDATE_FREQ_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SETDWC_pcie_wire_cpcie_usp_4x8.csr19347UPDATE_FREQ_TIMER is an internally reserved field. Do not use.Note: This register field is sticky.28240x00R/WFAST_LINK_SCALING_FACTORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr19369Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Factor is 64 (1ms is 16us) - 3: Scaling Factor is 16 (1ms is 64us)Default is set by the hidden configuration parameter DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0'.*a. When the LTSSM is in Config or L12 Entry State, 1ms timer is 2us, 2ms timer is 4us and 3ms timer is 6us.Not used for M-PCIe. Note: This register field is sticky.30290x2R/WRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr19377Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFSYMBOL_TIMER_FILTER_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr195350x1CR/W0x00000140PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFFSymbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.falsefalsefalsefalseSKP_INT_VALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SETDWC_pcie_wire_cpcie_usp_4x8.csr19417SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register (in a 250 MHz controller), then the controller actually transmits SKP ordered sets once every 1537 symbol times.The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz controller, programming the value programmed to this register should be scaled down by a factor of 2 (because one clock tick = two symbol times in this case).Note: This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks.For M-PCIe configurations, if the 2K_PPM_DISABLED field in the M-PCIe Configuration Attribute is changed, then this field is changed automatically as follows. - 2K_PPM_DISABLED=1: 1280 / CX_NB - 2K_PPM_DISABLED=0: 228/CX_NBYou need to set this field again if necessary when 2K_PPM_DISABLED is changed.Note: This register field is sticky.1000x140R/WEIDLE_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SETDWC_pcie_wire_cpcie_usp_4x8.csr19426EIDLE_TIMER is an internally reserved field. Do not use.Note: This register field is sticky.14110x0R/WDISABLE_FC_WD_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SETDWC_pcie_wire_cpcie_usp_4x8.csr19435Disable FC Watchdog Timer.Note: This register field is sticky.15150x0R/WMASK_RADM_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr19534Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.[31]: CX_FLT_MASK_RC_CFG_DISCARD - 0: For RADM RC filter to not allow CFG transaction being received - 1: For RADM RC filter to allow CFG transaction being received[30]: CX_FLT_MASK_RC_IO_DISCARD - 0: For RADM RC filter to not allow IO transaction being received - 1: For RADM RC filter to allow IO transaction being received[29]: CX_FLT_MASK_MSG_DROP - 0: Drop MSG TLP (except for Vendor MSG). Send decoded message on the SII. - 1: Do not Drop MSG (except for Vendor MSG). Send message TLPs to your application on TRGT1 and send decoded message on the SII. - The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG =1, then the default of this bit is "0" (drop message TLPs). This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The controller never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The controller passes all ATS Invalidate messages to TRGT1 (or AXI bridge master), as they are too big for the SII.[28]: CX_FLT_MASK_CPL_ECRC_DISCARD - Only used when completion queue is advertised with infinite credits and is in store-and-forward mode. - 0: Discard completions with ECRC errors - 1: Allow completions with ECRC errors to be passed up - Reserved field for SW.[27]: CX_FLT_MASK_ECRC_DISCARD - 0: Discard TLPs with ECRC errors - 1: Allow TLPs with ECRC errors to be passed up[26]: CX_FLT_MASK_CPL_LEN_MATCH - 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err - 1: MASK length match for completions[25]: CX_FLT_MASK_CPL_ATTR_MATCH - 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask attribute match for completions[24]: CX_FLT_MASK_CPL_TC_MATCH - 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Traffic Class match for completions[23]: CX_FLT_MASK_CPL_FUNC_MATCH - 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask function match for completions[22]: CX_FLT_MASK_CPL_REQID_MATCH - 0: Enforce Req. Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Req. Id match for completions[21]: CX_FLT_MASK_CPL_TAGERR_MATCH - 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Tag Error Rules for completions[20]: CX_FLT_MASK_LOCKED_RD_AS_UR - 0: Treat locked Read TLPs as UR for EP; Supported for RC - 1: Treat locked Read TLPs as Supported for EP; UR for RC[19]: CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR - 0: Treat CFG type1 TLPs as UR for EP; Supported for RC - 1: Treat CFG type1 TLPs as Supported for EP; UR for RC - When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests if the EP consumes more than one bus number.[18]: CX_FLT_MASK_UR_OUTSIDE_BAR - 0: Treat out-of-bar TLPs as UR - 1: Do not treat out-of-bar TLPs as UR[17]: CX_FLT_MASK_UR_POIS - 0: Treat poisoned request TLPs as UR - 1: Do not treat poisoned request TLPs as UR - The native controller always passes poisoned completions to your application except when you are using the DMA read channel.[16]: CX_FLT_MASK_UR_FUNC_MISMATCH - 0: Treat Function MisMatched TLPs as UR - 1: Do not treat Function MisMatched TLPs as URNote: This register field is sticky.31160x0000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFFILTER_MASK_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr195960x20R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_FILTER_MASK_2_OFFFilter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.falsefalsefalsefalseMASK_RADM_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr19595Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.[31:10]: Reserved[9]: CX_FLT_MASK_CPL_IN_LUT_CHECK - 0: Disable masking of checking if the tag of CPL is registered in LUT - 1: Enable masking of checking if the tag of CPL is registered in LUT[8]: CX_FLT_MASK_POIS_ERROR_REPORTING - 0: Disable masking of error reporting for Poisoned TLPs - 1: Enable masking of error reporting for Poisoned TLPs[7]: CX_FLT_MASK_PRS_DROP - 0: Allow PRS message to pass through - 1: Drop PRS Messages silently - This bit is ignored when the CX_FLT_MASK_MSG_DROP bit in the MASK_RADM_1 field of the SYMBOL_TIMER_FILTER_1_OFF register is set to '1'.[6]: CX_FLT_UNMASK_TD - 0: Disable unmask TD bit if CX_STRIP_ECRC_ENABLE - 1: Enable unmask TD bit if CX_STRIP_ECRC_ENABLE[5]: CX_FLT_UNMASK_UR_POIS_TRGT0 - 0: Disable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination - 1: Enable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination[4]: CX_FLT_MASK_LN_VENMSG1_DROP - 0: Allow LN message to pass through - 1: Drop LN Messages silently[3]: CX_FLT_MASK_HANDLE_FLUSH - 0: Disable controller Filter to handle flush request - 1: Enable controller Filter to handle flush request[2]: CX_FLT_MASK_DABORT_4UCPL - 0: Enable DLLP abort for unexpected completion - 1: Do not enable DLLP abort for unexpected completion[1]: CX_FLT_MASK_VENMSG1_DROP - 0: Vendor MSG Type 1 dropped silently - 1: Vendor MSG Type 1 not dropped[0]: CX_FLT_MASK_VENMSG0_DROP - 0: Vendor MSG Type 0 dropped with UR error reporting - 1: Vendor MSG Type 0 not droppedNote: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFAMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr196300x24R/W0x00000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFAMBA Multiple Outbound Decomposed NP SubRequests Control Register.falsefalsefalsefalseOB_RD_SPLIT_BURST_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr19621Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to "0" disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more details, see "AXI Bridge Ordering" in the AXI chapter of the Databook.You should not clear this register unless your application master is requesting an amount of read data greater than Max_Read_Request_Size, and the remote device (or switch) is reordering completions that have different tags.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr19629Reserved for future use.3110x00000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFPL_DEBUG0_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr196430x28RPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PL_DEBUG0_OFFDebug Register 0falsefalsefalsefalseDEB_REG_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr19642The value on cxpl_debug_info[31:0].310RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFPL_DEBUG1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr196560x2CRPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PL_DEBUG1_OFFDebug Register 1falsefalsefalsefalseDEB_REG_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr19655The value on cxpl_debug_info[63:32].310RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFTX_P_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr197100x30R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFFTransmit Posted FC Credit StatusfalsefalsefalsefalseTX_P_DATA_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr19681Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_P_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr19702Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_P_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr19709Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFTX_NP_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr197640x34R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFFTransmit Non-Posted FC Credit StatusfalsefalsefalsefalseTX_NP_DATA_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr19735Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_NP_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr19756Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_NP_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr19763Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFTX_CPL_FC_CREDIT_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr198180x38R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFFTransmit Completion FC Credit StatusfalsefalsefalsefalseTX_CPL_DATA_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr19789Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_CPL_HEADER_FC_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr19810Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_CPL_FC_CREDIT_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr19817Reserved for future use.31280x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFQUEUE_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr199220x3CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_QUEUE_STATUS_OFFQueue StatusfalsefalsefalsefalseRX_TLP_FC_CREDIT_NON_RETURNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SETDWC_pcie_wire_cpcie_usp_4x8.csr19835Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the link.000x0RTX_RETRY_BUFFER_NEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SETDWC_pcie_wire_cpcie_usp_4x8.csr19846Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer.110x0RRX_QUEUE_NON_EMPTYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SETDWC_pcie_wire_cpcie_usp_4x8.csr19857Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers.220x0RRX_QUEUE_OVERFLOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SETDWC_pcie_wire_cpcie_usp_4x8.csr19868Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue.330x0R/W1CRSVDP_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr19876Reserved for future use.1240x000RRX_SERIALIZATION_Q_NON_EMPTYPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SETDWC_pcie_wire_cpcie_usp_4x8.csr19887Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue.13130x0R--15140x0rTIMER_MOD_FLOW_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SETDWC_pcie_wire_cpcie_usp_4x8.csr19900FC Latency Timer Override Value. When you set the "FC Latency Timer Override Enable" in this register, the value in this field will override the FC latency timer value that the controller calculates according to the PCIe specification. For more details, see "Flow Control".Note: This register field is sticky.28160x0000R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr19908Reserved for future use.30290x0RTIMER_MOD_FLOW_CONTROL_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr19921FC Latency Timer Override Enable. When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will override the FC latency timer value that the controller calculates according to the PCIe specification.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFVC_TX_ARBI_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr199710x40R0x0000000fPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFFVC Transmit Arbitration Register 1falsefalsefalsefalseWRR_WEIGHT_VC_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr19937WRR Weight for VC0.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 700x0fRWRR_WEIGHT_VC_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr19948WRR Weight for VC1.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 1580x00RWRR_WEIGHT_VC_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr19959WRR Weight for VC2.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 23160x00RWRR_WEIGHT_VC_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr19970WRR Weight for VC3.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFVC_TX_ARBI_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr200200x44R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFFVC Transmit Arbitration Register 2falsefalsefalsefalseWRR_WEIGHT_VC_4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr19986WRR Weight for VC4.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 700x00RWRR_WEIGHT_VC_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr19997WRR Weight for VC5.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 1580x00RWRR_WEIGHT_VC_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr20008WRR Weight for VC6.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 23160x00RWRR_WEIGHT_VC_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr20019WRR Weight for VC7.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 31240x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFVC0_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr201240x48R/W0x462602e0PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFFSegmented-Buffer VC0 Posted Receive Queue Control.falsefalsefalsefalseVC0_P_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20037VC0 Posted Data Credits. The number of initial posted data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC0_P_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20051VC0 Posted Header Credits. The number of initial posted header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED4PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SETDWC_pcie_wire_cpcie_usp_4x8.csr20060Reserved.Note: This register field is sticky.20200x0R/WVC0_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20069Reserved.Note: This register field is sticky.23210x1R/WVC0_P_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20079VC0 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC0_P_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20089VC0 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SETDWC_pcie_wire_cpcie_usp_4x8.csr20098Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr20110TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WVC_ORDERING_RX_QPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SETDWC_pcie_wire_cpcie_usp_4x8.csr20123VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0: Round robinNote: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFVC0_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr202030x4CR/W0x06260060PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFFSegmented-Buffer VC0 Non-Posted Receive Queue Control.falsefalsefalsefalseVC0_NP_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20141VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x060R/WVC0_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20155VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SETDWC_pcie_wire_cpcie_usp_4x8.csr20164Reserved.Note: This register field is sticky.20200x0R/WVC0_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20173Reserved.Note: This register field is sticky.23210x1R/WVC0_NP_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20183VC0 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC0_NP_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20193VC0 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SETDWC_pcie_wire_cpcie_usp_4x8.csr20202Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFVC0_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr202820x50R/W0x06200000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC0 Completion Receive Queue Control.falsefalsefalsefalseVC0_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20220VC0 Completion Data Credits. The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC0_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20234VC0 Completion Header Credits. The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SETDWC_pcie_wire_cpcie_usp_4x8.csr20243Reserved.Note: This register field is sticky.20200x0R/WVC0_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20252Reserved.Note: This register field is sticky.23210x1R/WVC0_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20262VC0 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC0_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20272VC0 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SETDWC_pcie_wire_cpcie_usp_4x8.csr20281Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFVC1_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr203820x54R/W0x462602e0PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC1_P_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20299VC1 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC1_P_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20313VC1 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr20322Reserved.Note: This register field is sticky.20200x0R/WVC1_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20331Reserved.Note: This register field is sticky.23210x1R/WVC1_P_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20341VC1 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC1_P_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20351VC1 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr20360Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr20372TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr20381Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFVC1_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr204610x58R/W0x06260001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC1_NP_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20399VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC1_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20413VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr20422Reserved.Note: This register field is sticky.20200x0R/WVC1_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20431Reserved.Note: This register field is sticky.23210x1R/WVC1_NP_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20441VC1 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC1_NP_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20451VC1 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr20460Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFVC1_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr205400x5CR/W0x06200000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC1_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20478VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC1_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20492VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr20501Reserved.Note: This register field is sticky.20200x0R/WVC1_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20510Reserved.Note: This register field is sticky.23210x1R/WVC1_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20520VC1 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC1_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20530VC1 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr20539Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFVC2_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr206400x60R/W0x462602e0PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC2_P_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20557VC2 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC2_P_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20571VC2 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr20580Reserved.Note: This register field is sticky.20200x0R/WVC2_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20589Reserved.Note: This register field is sticky.23210x1R/WVC2_P_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20599VC2 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC2_P_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20609VC2 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr20618Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr20630TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr20639Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFVC2_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr207190x64R/W0x06260001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC2_NP_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20657VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC2_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20671VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr20680Reserved.Note: This register field is sticky.20200x0R/WVC2_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20689Reserved.Note: This register field is sticky.23210x1R/WVC2_NP_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20699VC2 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC2_NP_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20709VC2 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr20718Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFVC2_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr207980x68R/W0x06200000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC2_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20736VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC2_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20750VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr20759Reserved.Note: This register field is sticky.20200x0R/WVC2_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20768Reserved.Note: This register field is sticky.23210x1R/WVC2_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20778VC2 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC2_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20788VC2 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr20797Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFVC3_P_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr208980x6CR/W0x462602e0PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC3_P_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20815VC3 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC3_P_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20829VC3 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr20838Reserved.Note: This register field is sticky.20200x0R/WVC3_P_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20847Reserved.Note: This register field is sticky.23210x1R/WVC3_P_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20857VC3 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC3_P_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20867VC3 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr20876Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr20888TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr20897Reserved.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFVC3_NP_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr209770x70R/W0x06260001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC3_NP_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20915VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC3_NP_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20929VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr20938Reserved.Note: This register field is sticky.20200x0R/WVC3_NP_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20947Reserved.Note: This register field is sticky.23210x1R/WVC3_NP_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20957VC3 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC3_NP_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr20967VC3 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr20976Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFVC3_CPL_RX_Q_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr210560x74R/W0x06200000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC3_CPL_DATA_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr20994VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC3_CPL_HEADER_CREDITPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr21008VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr21017Reserved.Note: This register field is sticky.20200x0R/WVC3_CPL_TLP_Q_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr21026Reserved.Note: This register field is sticky.23210x1R/WVC3_CPL_HDR_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr21036VC3 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC3_CPL_DATA_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr21046VC3 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr21055Reserved.Note: This register field is sticky.31280x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFGEN2_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr21342Link Width and Speed Change Control Register.0x10CR/W0x000108c8PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN2_CTRL_OFFThis register is used to control various functions of the controller related to link training, lane reversal, and equalization.falsefalsefalsefalseFAST_TRAINING_SEQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr21083Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state. The number should be provided by the PHY vendor. Do not set N_FTS to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.700xc8R/WNUM_OF_LANESPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_SETDWC_pcie_wire_cpcie_usp_4x8.csr21123Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured. This value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI Express Base 3.0 Specification, revision 1.0. Encoding is as follows: - 0x01: 1 lane - 0x02: 2 lanes - 0x03: 3 lanes - ..When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Link Mode Enable" field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as the encoded value in PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then you must reduce the value in this register. For more information, see "How to Tie Off Unused Lanes." For information on upsizing and downsizing the link width, see "Link Establishment."This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.1280x08R/WPRE_DET_LANEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_SETDWC_pcie_wire_cpcie_usp_4x8.csr21173Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect.This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state.Note: This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.15130x0R/WfalsetruefalseLANE00x0Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1, depending on which lane is detectedLANE10x1Connect logical Lane0 to physical lane 1LANE150x4Connect logical Lane0 to physical lane 15LANE30x2Connect logical Lane0 to physical lane 3LANE70x3connect logical lane0 to physical lane 7AUTO_LANE_FLIP_CTRL_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr21191Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details, see the 'Lane Reversal' appendix in the Databook. This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.16160x1R/WDIRECT_SPEED_CHANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SETDWC_pcie_wire_cpcie_usp_4x8.csr21224Directed Speed Change. Writing "1" to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed.When the speed change occurs, the controller will clear the contents of this field; and a read to this field by your software will return a "0".To manually initiate the speed change: - Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this fieldIf you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1", then the speed change is initiated automatically after link up, and the controller clears the contents of this field. If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF . PCIE_CAP_TARGET_LINK_SPEED) through the DBI before link up.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 17170x0R/WCONFIG_PHY_TX_CHANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SETDWC_pcie_wire_cpcie_usp_4x8.csr21241Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low SwingThis field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.18180x0R/WCONFIG_TX_COMP_RXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SETDWC_pcie_wire_cpcie_usp_4x8.csr21256Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to "1").This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WSEL_DEEMPHASISPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SETDWC_pcie_wire_cpcie_usp_4x8.csr21272Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dBThis field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.20200x0R/WGEN1_EI_INFERENCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr21290Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be inferred successfully in the controller by just detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical IdleNote: This register field is sticky.21210x0R/WRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr21298Reserved for future use.23220x0RLANE_UNDER_TESTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_SETDWC_pcie_wire_cpcie_usp_4x8.csr21315The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.27240x0R--29280x0rFORCE_LANE_FLIPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_SETDWC_pcie_wire_cpcie_usp_4x8.csr21333Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.30300x0RRSVDP_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr21341Reserved for future use.31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFPHY_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr213660x110RPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PHY_STATUS_OFFPHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins.falsefalsefalsefalsePHY_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr21365PHY Status. Data received directly from the phy_cfg_status bus.These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller functionality. You can use it for any static sideband status signalling requirements that you have for your PHY.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.310RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFPHY_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr213880x114R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PHY_CONTROL_OFFPHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins.falsefalsefalsefalsePHY_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_SETDWC_pcie_wire_cpcie_usp_4x8.csr21387PHY Control. Data sent directly to the cfg_phy_control bus.These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller functionality. You can use it for any static sideband control signalling requirements that you have for your PHY.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFTRGT_MAP_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr214470x11CR/W0x0000006fPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFFProgrammable Target Map Control Register.falsefalsefalsefalseTARGET_MAP_PFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SETDWC_pcie_wire_cpcie_usp_4x8.csr21401Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits.500x2fR/WTARGET_MAP_ROMPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SETDWC_pcie_wire_cpcie_usp_4x8.csr21412Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits.660x1R/W--1270x0rTARGET_MAP_RESERVED_13_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr21424Reserved.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R (sticky) 15130x0RTARGET_MAP_INDEXPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SETDWC_pcie_wire_cpcie_usp_4x8.csr21434The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits.20160x00R/WTARGET_MAP_RESERVED_21_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr21446Reserved.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R (sticky) 31210x000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFMSI_CTRL_ADDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr214670x120R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFFIntegrated MSI Reception Module (iMRM) Address Register.falsefalsefalsefalseMSI_CTRL_ADDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_SETDWC_pcie_wire_cpcie_usp_4x8.csr21466Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination.Within the AXI Bridge, every received Memory Write request is examined to see if it targets the MSI Address that has been specified in this register; and also to see if it satisfies the definition of an MSI interrupt request. When these conditions are satisfied the Memory Write request is marked as an MSI request.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFMSI_CTRL_UPPER_ADDR_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr214830x124R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFFIntegrated MSI Reception Module Upper Address Register.falsefalsefalsefalseMSI_CTRL_UPPER_ADDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_SETDWC_pcie_wire_cpcie_usp_4x8.csr21482Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFMSI_CTRL_INT_0_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr215000x128R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_0_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr21499MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFMSI_CTRL_INT_0_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr215180x12CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_0_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr21517MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFMSI_CTRL_INT_0_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr215360x130R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_0_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr21535MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFMSI_CTRL_INT_1_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr215530x134R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_1_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr21552MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFMSI_CTRL_INT_1_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr215710x138R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_1_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr21570MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFMSI_CTRL_INT_1_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr215890x13CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_1_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr21588MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFMSI_CTRL_INT_2_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr216060x140R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_2_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr21605MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFMSI_CTRL_INT_2_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr216240x144R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_2_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr21623MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFMSI_CTRL_INT_2_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr216420x148R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_2_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr21641MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFMSI_CTRL_INT_3_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr216590x14CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_3_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr21658MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFMSI_CTRL_INT_3_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr216770x150R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_3_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr21676MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFMSI_CTRL_INT_3_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr216950x154R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_3_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr21694MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFMSI_CTRL_INT_4_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr217120x158R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_4_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr21711MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFMSI_CTRL_INT_4_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr217300x15CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_4_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr21729MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFMSI_CTRL_INT_4_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr217480x160R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_4_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr21747MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFMSI_CTRL_INT_5_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr217650x164R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_5_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr21764MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFMSI_CTRL_INT_5_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr217830x168R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_5_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr21782MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFMSI_CTRL_INT_5_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr218010x16CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_5_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr21800MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFMSI_CTRL_INT_6_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr218180x170R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_6_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr21817MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFMSI_CTRL_INT_6_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr218360x174R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_6_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr21835MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFMSI_CTRL_INT_6_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr218540x178R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_6_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr21853MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFMSI_CTRL_INT_7_EN_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr218710x17CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_7_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr21870MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFMSI_CTRL_INT_7_MASK_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr218890x180R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_7_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr21888MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFMSI_CTRL_INT_7_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr219070x184R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_7_STATUSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr21906MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFMSI_GPIO_IO_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr219210x188R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSI_GPIO_IO_OFFIntegrated MSI Reception Module General Purpose IO Register.falsefalsefalsefalseMSI_GPIO_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_SETDWC_pcie_wire_cpcie_usp_4x8.csr21920MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0]Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFCLOCK_GATING_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr219890x18CR/W0x00000003PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFFThis register enables you to disable dynamic clock gating. By default dynamic clock gating is on, allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module, DWC_pcie_clk_rst.v, and is initiated by the controllers clock enable signals. The following modules support dynamic clock gating: - AXI Bridge - RADMfalsefalsefalsefalseRADM_CLK_GATING_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr21953RADM Clock Gating Enable. This register, if set, enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock, radm_clk_g, to the RADM and is enabled when the controllers clock enable signal, en_radm_clk_g, is asserted. The RADM clock is a gated version of the controller clock, core_clk. The controller de-asserts en_radm_clk_g when there is no Rx traffic, Rx queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR actions pending. - 0: Disable - 1: Enable (default)Note: This register field is sticky.000x1R/WAXI_CLK_GATING_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr21980AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock, the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock, mstr_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, mstr_aclk_active, is asserted. For the AXI Slave this module provides the gated clock, slv_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, slv_aclk_active, is asserted. If the AXI DBI Slave is enabled (DBI_4SLAVE_POPULATED=1) the module provides the gated clock, dbi_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, dbi_aclk_active, is asserted. The controller de-asserts the clock enable signals when the respective AXI Master/Slave interfaces are idle. - 0: Disable - 1: Enable (default)Note: This register field is sticky.110x1R/WRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr21988Reserved for future use.3120x00000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFGEN3_RELATED_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr223340x190R/W0x00402001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN3_RELATED_OFFGen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific "Directed Speed Change" field. The "Directed Speed Change" field in the "Link Width and Speed Change Control Register" is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the "Directed Speed Change" field is set to "1" and (2) the "Target Link Speed" field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training.M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.falsefalsefalsefalseGEN3_ZRXDC_NONCOMPLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_SETDWC_pcie_wire_cpcie_usp_4x8.csr22024Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled. - 0: The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. - 1: The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rates.Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr22032Reserved for future use.710x00RDISABLE_SCRAMBLER_GEN_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr22047Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY).Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.880x0R/WEQ_PHASE_2_3PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr22068Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.990x0R/WEQ_EIEOS_CNTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr22082Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.10100x0R/WEQ_REDOPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_SETDWC_pcie_wire_cpcie_usp_4x8.csr22102Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is infinite or you do not want eq requests and redo, setting this bit to 1 will stop the EQ requests and EQ redo so that the link can go ahead to L0 state for packet trasmissions.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.11110x0R/WRXEQ_PH01_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr22133Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY. This bit is used during Virtex-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: - 00: Tx equalization only in phase 2/3 - 01: No Tx equalization, no Rx equalization - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/1 - 11: No Tx equalization, Rx equalization in phase 0/1Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.12120x0R/WRXEQ_RGRDLESS_RXTSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_SETDWC_pcie_wire_cpcie_usp_4x8.csr22159When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.13130x1R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr22167Reserved for future use.15140x0RGEN3_EQUALIZATION_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr22181Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.16160x0R/WGEN3_DLLP_XMT_DELAY_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr22195DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.17170x0R/WGEN3_DC_BALANCE_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr22207DC Balance Disable. Disable DC Balance feature.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.18180x0R/WRSVDP_19PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_SETDWC_pcie_wire_cpcie_usp_4x8.csr22215Reserved for future use.20190x0RAUTO_EQ_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr22242Autonomous Equalization Disable. When the controller is in L0 state at Gen3 data rate and equalization was completed successfully in Autonomous EQ Mechanism, setting this bit in DSP will not direct the controller to Recovery state to perform Gen4 equalization. Link stays in Gen3 rate and DSP sends DLLPs to USP. If the bit is 0, DSP will block DLLPs and direct the link to perform Gen4 EQ in Autonomous Mechanism.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.21210x0R/WUSP_SEND_8GT_EQ_TS2_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr22269Upstream Port Send 8GT/s or 16GT/s EQ TS2 Disable. The base spec defines that USP can optionally send 8GT or 16GT EQ TS2 and it means USP can set DSP TxPreset value in Gen4 or Gen5 Data Rate. If this register set to 0, USP sends 8GT or 16GT EQ TS2. If this register set to 1, USP does not send 8GT or 16GT EQ TS2. This applies to upstream ports only. No Function for downstream ports.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. Value after reset in Gen4/Gen5 is 0x1.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.22220x1R/WGEN3_EQ_INVREQ_EVAL_DIFF_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr22284Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.23230x0R/WRATE_SHADOW_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr22325Rate Shadow Select. This register value decide the Data Rate of shadow register. - 00b: Gen3 Data Rate is selected for shadow register. - 01b: Gen4 Data Rate is selected for shadow register. - 10b: Gen5 Data Rate is selected for shadow register. - 11b: Reserved.The following shadow registers are controlled by this register. - GEN3_RELATED_OFF[9] EQ_PHASE_2_3 - GEN3_RELATED_OFF[12] RXEQ_PH01_EN - GEN3_RELATED_OFF[19] RE_EQ_REQUEST_ENABLE - GEN3_RELATED_OFF[21] AUTO_EQ_DISABLE - GEN3_RELATED_OFF[22] USP_SEND_8GT_EQ_TS2_DISABLE - GEN3_EQ_LOCAL_FS_LF_OFF[5:0] GEN3_EQ_LOCAL_LF - GEN3_EQ_LOCAL_FS_LF_OFF[11:6] GEN3_EQ_LOCAL_FS - GEN3_EQ_PSET_COEFF_MAP_0[5:0] GEN3_EQ_PRE_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[11:6] GEN3_EQ_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[17:12] GEN3_EQ_POSET_CURSOR_PSET - GEN3_EQ_CONTROL_OFF[3:0] GEN3_EQ_FB_MODE - GEN3_EQ_CONTROL_OFF[4] GEN3_EQ_PHASE23_EXIT_MODE - GEN3_EQ_CONTROL_OFF[5] GEN3_EQ_EVAL_2MS_DISABLE - GEN3_EQ_CONTROL_OFF[23:8] GEN3_EQ_PSET_REQ_VEC - GEN3_EQ_CONTROL_OFF[24] GEN3_EQ_FOM_INC_INITIAL_EVAL - GEN3_EQ_CONTROL_OFF[25] GEN3_EQ_PSET_REQ_AS_COEF - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[4:0] GEN3_EQ_FMDC_T_MIN_PHASE23 - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[9:5] GEN3_EQ_FMDC_N_EVALS - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[13:10] GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[17:14] GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTANote: This register field is sticky.25240x0R/WRSVDP_26PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_SETDWC_pcie_wire_cpcie_usp_4x8.csr22333Reserved for future use.31260x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFGEN3_EQ_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr225660x1A8R/W0x05039f71PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFFGen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP).M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.falsefalsefalsefalseGEN3_EQ_FB_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr22362Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: ReservedNote: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.300x1R/WGEN3_EQ_PHASE23_EXIT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr22409Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 2 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 2 Complete status bit is set in the "Link Status Register 2"For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.RcvrLockWhen optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 3 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 3 Complete status bit is set in the "Link Status Register 2"Note: GEN3_EQ_PHASE23_EXIT_MODE = 1 affects Direction Change feed back mode. EQ requests for Figure Of Merit mode complete before 24 ms timeout. Please see GEN3_EQ_PSET_REQ_VEC Register for more.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.440x1R/WGEN3_EQ_EVAL_2MS_DISABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr22433Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout - 1: ignore the 2ms timeout and continue as normal. This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.550x1R/WGEN3_LOWER_RATE_EQ_REDO_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr22447Support EQ redo and lower rate change: - 0: not support - 1: supportNote: Gen3 and Gen4 share the same register bit and have the same feature.Note: This register field is sticky.660x1R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr22455Reserved for future use.770x0RGEN3_EQ_PSET_REQ_VECPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_SETDWC_pcie_wire_cpcie_usp_4x8.csr22510Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase. - 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: Preset 0 is requested and evaluated in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase - 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase - 000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase - All other encodings: ReservedNote: You must contact your PHY vendor to ensure 24 ms timeout does not occur in presets requests in EQ master phase, i.e., you must set a proper value to the GEN3_EQ_PSET_REQ_VEC register so that the EQ tunning for Figure of Merit in the EQ master phase completes before 24 ms timeout.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.2380x039fR/WGEN3_EQ_FOM_INC_INITIAL_EVALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_SETDWC_pcie_wire_cpcie_usp_4x8.csr22530Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: IncludeNote: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.24240x1R/WGEN3_EQ_PSET_REQ_AS_COEFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_SETDWC_pcie_wire_cpcie_usp_4x8.csr22541GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use.Note: This register field is sticky.25250x0R/WGEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr22557Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: requestNote: Gen3 and Gen4 share the same register bit and have the same feature.Note: This register field is sticky.26260x1R/WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr22565Reserved for future use.31270x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFGEN3_EQ_FB_MODE_DIR_CHANGE_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr226720x1ACR/W0x00000040PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFFGen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feedback Mode in "Gen3 EQ Control Register" to "Direction Change." These fields allow control over the initial starting point for the search of optimal coefficient settings, and allow control over the criteria used to determine when the optimal settings have been achieved. The values are applied to all the lanes.falsefalsefalsefalseGEN3_EQ_FMDC_T_MIN_PHASE23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_SETDWC_pcie_wire_cpcie_usp_4x8.csr22597Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time, before starting to check for convergence of the coefficients.Allowed values 0,1,...,24.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.400x00R/WGEN3_EQ_FMDC_N_EVALSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_SETDWC_pcie_wire_cpcie_usp_4x8.csr22624Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found.Allowed range: 0,1,2,..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH.When set to 0, EQ Master is performed without sending any requests to the remote partner in Phase 2 for USP and Phase 3 for DSP. Therefore, the remote partner will not change its transmitter coefficients and will move to the next state.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.950x02R/WGEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_SETDWC_pcie_wire_cpcie_usp_4x8.csr22644Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth.Allowed range: 0,1,2,..15.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.13100x0R/WGEN3_EQ_FMDC_MAX_POST_CUSROR_DELTAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_SETDWC_pcie_wire_cpcie_usp_4x8.csr22663Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.17140x0R/WRSVDP_18PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr22671Reserved for future use.31180x0000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFORDER_RULE_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr227060x1B4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFFOrder Rule Control Register.falsefalsefalsefalseNP_PASS_PPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_SETDWC_pcie_wire_cpcie_usp_4x8.csr22686Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P700x00R/WCPL_PASS_PPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SETDWC_pcie_wire_cpcie_usp_4x8.csr22697Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P1580x00R/WRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr22705Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFPIPE_LOOPBACK_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr227620x1B8R/W0x000000ffPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFFPIPE Loopback Control Register.falsefalsefalsefalseLPBK_RXVALIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SETDWC_pcie_wire_cpcie_usp_4x8.csr22718LPBK_RXVALID is an internally reserved field. Do not use.Note: This register field is sticky.1500x00ffR/WRXSTATUS_LANEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SETDWC_pcie_wire_cpcie_usp_4x8.csr22727RXSTATUS_LANE is an internally reserved field. Do not use.Note: This register field is sticky.21160x00R/WRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr22735Reserved for future use.23220x0RRXSTATUS_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr22744RXSTATUS_VALUE is an internally reserved field. Do not use.2624WRSVDP_27PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr22752Reserved for future use.30270x0RPIPE_LOOPBACKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SETDWC_pcie_wire_cpcie_usp_4x8.csr22761PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe.Note: This register field is sticky.31310x0R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFMISC_CONTROL_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr229560x1BCR/W0x0007ff48PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MISC_CONTROL_1_OFFDBI Read-Only Write Enable Register.falsefalsefalsefalseDBI_RO_WR_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr22780Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'.For more details, see "Writing to Read-Only Registers" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.Note: This register field is sticky.000x0R/WDEFAULT_TARGETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SETDWC_pcie_wire_cpcie_usp_4x8.csr22801Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion with UR status is generated for non-posted requests. - 1: The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application.For more details, see "ECRC Handling" and "Request TLP Routing Rules" in "Receive Routing" section of the "Controller Operations" chapter of the Databook.Note: This register field is sticky.110x0R/WUR_CA_MASK_4_TRGT1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr22815When this field is set to '1', the controller suppresses error logging, error message generation, and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is, when DEFAULT_TARGET =1). For more details, see "Advanced Error Handling For Received TLPs" chapter of the Databook.Note: This register field is sticky.220x0R/WSIMPLIFIED_REPLAY_TIMERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SETDWC_pcie_wire_cpcie_usp_4x8.csr22834Enables Simplified Replay Timer (Gen4). For more details, see "Transmit Replay" in "Transmit TLP Processing" section in the "Controller Operations" chapter of the Databook.Simplified Replay Timer can have the following Values: - A value from 24,000 to 31,000 Symbol Times when Extended Synch is 0b. - A value from 80,000 to 100,000 Symbol Times when Extended Synch is 1b.The Simplified Replay Timer value must not be changed while the link is in use.Note: This register field is sticky.330x1R/WDISABLE_AUTO_LTR_CLR_MSGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_SETDWC_pcie_wire_cpcie_usp_4x8.csr22852Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear message.For more details, see "Latency Tolerance Reporting (LTR) Message Generation[EP Mode]" in "Message Generation" section of the "Controller Operations" chapter of the Databook.Note: This register field is sticky.440x0R/WARI_DEVICE_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr22862When ARI is enabled, this field enables use of the device ID.Note: This register field is sticky.550x0R/WCPLQ_MNG_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr22872This field enables the Completion Queue Management feature.Note: This register field is sticky.660x1R/WCFG_TLP_BYPASS_EN_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_SETDWC_pcie_wire_cpcie_usp_4x8.csr22891Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to the setting of TARGET_ABOVE_CONFIG_LIMIT_REG - 1: Configuration TLPs are routed according to the setting of CONFIG_LIMIT_REGNote: When app_req_retry_en is asserted, the setting of this field is ignored.Note: This register field is sticky.770x0R/WCONFIG_LIMIT_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_SETDWC_pcie_wire_cpcie_usp_4x8.csr22912Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of TARGET_ABOVE_CONFIG_LIMIT_REG field.Your application must set a proper value for this field based on your extended configuration registers. For more details, see the "CDM/ELBI Register Space Access Through CFG Request" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.Note: This register field is sticky.1780x3ffR/WTARGET_ABOVE_CONFIG_LIMIT_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_SETDWC_pcie_wire_cpcie_usp_4x8.csr22925Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1Note: This register field is sticky.19180x1R/WP2P_TRACK_CPL_TO_REGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_SETDWC_pcie_wire_cpcie_usp_4x8.csr22936Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reportingNote: This register field is sticky.20200x0R/WP2P_ERR_RPT_CTRLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_SETDWC_pcie_wire_cpcie_usp_4x8.csr22947Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completionNote: This register field is sticky.21210x0R/WRSVDP_22PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr22955Reserved for future use.31220x000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFMULTI_LANE_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr230300x1C0R/W0x00000080PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFFUpConfigure Multi-lane Control Register.Used when upsizing or downsizing the link width through Configuration state without bringing the link down.For more details, see the "Link Establishment" section in the "ControllerOperations" chapter of the Databook.falsefalsefalsefalseTARGET_LINK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr22983Target Link Width.Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 - 6'b100000: x32This field is reserved (fixed to '0') for M-PCIe.500x00R/WDIRECT_LINK_WIDTH_CHANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SETDWC_pcie_wire_cpcie_usp_4x8.csr23006Directed Link Width Change.The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the controller starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the controller does not start upconfigure or autonomous width downsizing in the Configuration state.The controller self-clears this field when the controller accepts this request.This field is reserved (fixed to '0') for M-PCIe.660x0R/WUPCONFIGURE_SUPPORTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr23021Upconfigure Support.The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.770x1R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr23029Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFPHY_INTEROP_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr231460x1C4R/W0x00000a44PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFFPHY Interoperability Control Register.falsefalsefalsefalseRXSTANDBY_CONTROLPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SETDWC_pcie_wire_cpcie_usp_4x8.csr23059Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP2 - [4]: RxL0s.Idle - [5]: EI Infer in L0 - [6]: Execute RxStandby/RxStandbyStatus HandshakeThis field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.600x44R/WRSVDP_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr23067Reserved for future use.770x0RL1SUB_EXIT_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr23084L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for the PHY to assert phy_mac_pclkack_n. - 0: Controller waits for the PHY to assert phy_mac_pclkack_n before exiting L1.Note: This register field is sticky.880x0R/WL1_NOWAIT_P1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SETDWC_pcie_wire_cpcie_usp_4x8.csr23105L1 entry control bit. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Controller waits for the PHY to acknowledge transition to P1 before entering L1.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.990x1RL1_CLK_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr23122L1 Clock control bit. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in L1. - 0: Controller requests aux_clk switch and core_clk gating in L1.Note: This register field is sticky.10100x0R/WP2NOBEACON_ENABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr23137P2.NoBeacon Enable bit. - 1: Controller drives P2.NoBeacon encoding for PHY power down state, when the link goes to L2. - 0: Controller drives P2 encoding for PHY power down state, when the link goes to L2.Note:This field is reserved (fixed to '0') if CX_P2NOBEACON_ENABLE is not set.Note: This register field is sticky.11110x1R/WRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr23145Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFTRGT_CPL_LUT_DELETE_ENTRY_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr231820x1C8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFFTRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion because of an FLR or any other reason.Note:: The target completion LUT (and associated target completion timeout event) is watching for completions (from your application on XALI0/1/2 or AXI master read channel) corresponding to previously received non-posted requests from the PCIe wire.falsefalsefalsefalseLOOK_UP_IDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr23168This number selects one entry to delete of the TRGT_CPL_LUT.3000x00000000R/WDELETE_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr23181This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field.This is a self-clearing register field. Reading from this register field always returns a '0'.31310x0WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFLINK_FLUSH_CONTROL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr232280x1CCR/W0xff000001PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFFLink Reset Request Flush Control Register.falsefalsefalsefalseAUTO_FLUSH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr23210Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge.The flushing process is initiated if any of the following events occur: - Hot reset request. A downstream port (DSP) can "hot reset" an upstream port (USP) by sending two consecutive TS1 ordered sets with the hot reset bit asserted. - Warm (Soft) reset request. Generated when exiting from D3 to D0 and cfg_pm_no_soft_rst=0. - Link down reset request. A high to low transition on smlh_req_rst_not indicates the link has gone down and the controller is requesting a reset.If you disable automatic flushing, your application is responsible for resetting the PCIe controller and the AXI Bridge. For more details see "Warm and Hot Resets" section in the Architecture chapter of the Databook.Note: This register field is sticky.000x1R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr23218Reserved for future use.2310x000000RRSVD_I_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr23227This is an internally reserved field. Do not use.Note: This register field is sticky.31240xffR/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFAMBA_ERROR_RESPONSE_DEFAULT_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr23358AXI Bridge Slave Error Response Register.0x1D0R/W0x00009c00PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFFAXI Bridge Slave Error Response Register.falsefalsefalsefalseAMBA_ERROR_RESPONSE_GLOBALPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SETDWC_pcie_wire_cpcie_usp_4x8.csr23257Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - 0: OKAY (with FFFF data for non-posted requests) and ignore the setting in bit [2] of this register. - 1: ERROR for normal link (data) accesses and look at bit [2] for other scenarios.AXI: - 0: OKAY (with FFFF data for non-posted requests) - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)The error response mapping is not applicable to Non-existent Vendor ID register reads.Note: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr23265Reserved for future use.110x0RAMBA_ERROR_RESPONSE_VENDORIDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SETDWC_pcie_wire_cpcie_usp_4x8.csr23284Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - 0: OKAY (with FFFF data). The controller ignores the setting in the bit when bit 0 of this register is '0'. - 1: ERRORAXI: - 0: OKAY (with FFFF data). - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)Note: This register field is sticky.220x0R/WAMBA_ERROR_RESPONSE_CRSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SETDWC_pcie_wire_cpcie_usp_4x8.csr23306CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - always returns OKAYAXI: - 00: OKAY - 01: OKAY with all FFFF_FFFF data for all CRS completions - 10: OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with FFFF_FFFF data for all other CRS completions - 11: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)Note: This register field is sticky.430x0R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr23314Reserved for future use.950x00RAMBA_ERROR_RESPONSE_MAPPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr23349AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses, slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is always mapped to OKAY. - [0] -- 0: UR (unsupported request) -> DECERR -- 1: UR (unsupported request) -> SLVERR - [1] -- 0: CRS (configuration retry status) -> DECERR -- 1: CRS (configuration retry status) -> SLVERR - [2] -- 0: CA (completer abort) -> DECERR -- 1: CA (completer abort) -> SLVERR - [3]: Reserved - [4]: Reserved - [5]: -- 0: Completion Timeout -> DECERR -- 1: Completion Timeout -> SLVERRThe AXI bridge internally drops (processes internally but not passed to your application) a completion that has been marked by the Rx filter as UC or MLF, and does not pass its status directly down to the slave interface. It waits for a timeout and then signals "Completion Timeout" to the slave interface.The controller sets the AXI slave read databus to 0xFFFF for all error responses.Note: This register field is sticky.15100x27R/WRSVDP_16PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr23357Reserved for future use.31160x0000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFAMBA_LINK_TIMEOUT_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr234050x1D4R/W0x00000032PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFFLink Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational, the controller starts a "flush" timer. The timeout value of the timer is set by this register. If the timer times out before the PCIe link is operational, the bridge TX request queues are flushed. For more details, see the "AXI Bridge Initialization, Clocking and Reset" section in the AXI chapter of the Databook.falsefalsefalsefalseLINK_TIMEOUT_PERIOD_DEFAULTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SETDWC_pcie_wire_cpcie_usp_4x8.csr23386Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not transmitting any of these requests.The timer is clocked by core_clk. For an M-PCIe configuration: - Time unit of this field is 4 ms. - Margin of error for RateA clock is < 1%. - Margin of error for RateB clock is between 16% and 17%.Note: This register field is sticky.700x32R/WLINK_TIMEOUT_ENABLE_DEFAULTPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SETDWC_pcie_wire_cpcie_usp_4x8.csr23396Disable Flush. You can disable the flush feature by setting this field to "1".Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr23404Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFAMBA_ORDERING_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr235150x1D8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFFAMBA Ordering Control.falsefalsefalsefalseRSVDP_0PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr23416Reserved for future use.000x0RAX_SNP_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr23430AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR and WAW hazards at the remote link partner. For more details, see the "Optional Serialization of AXI Slave Non-posted Requests" section in the AXI chapter of the Databook.110x0R/WRSVDP_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr23438Reserved for future use.220x0RAX_MSTR_ORDR_P_EVENT_SELPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr23482AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule, "NP must not pass P" at the AXI Master Interface.The AXI protocol does not support ordering between channels. Therefore, NP reads can pass P on your AXI bus fabric. This can result in an ordering violation when the read overtakes a P that is going to the same address. Therefore, the bridge master does not issue any NP requests until all outstanding P writes reach their destination. It does this by waiting for the all of the write responses on the B channel. This can affect the performance of the master read channel.For scenarios where the interconnect serializes the AXI master "AW", "W" and "AR" channels,you can increase the performance by reducing the need to wait until the complete Posted transaction has effectively reached the application slave. - 00: B'last event: wait for the all of the write responses on the B channel thereby ensuring that the complete Posted transaction has effectively reached the application slave (default). - 01: AW'last event: wait until the complete Posted transaction has left the AXI address channel at the bridge master. - 10: W'last event: wait until the complete Posted transaction has left the AXI data channel at the bridge master. - 11: ReservedNote 2: This setting will not affect: - MSI interrupt catcher and P data ordering. This is always driven by the B'last event. - DMA read engine TLP ordering. This is always driven by the B'last event. - NP write transactions which are always serialized with P write transactions.430x0R/WRSVDP_5PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr23490Reserved for future use.650x0RAX_MSTR_ZEROLREAD_FWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SETDWC_pcie_wire_cpcie_usp_4x8.csr23506AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read, implementing the PCIe express flush semantics of the Posted transactions. - 0x0: The zero length Read is terminated at the DW PCIe AXI bridge master - 0x1: The zero length Read is forward to the application.770x0R/WRSVDP_8PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr23514Reserved for future use.3180x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFCOHERENCY_CONTROL_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr235520x1E0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFFACE Cache Coherency Control Register 1falsefalsefalsefalseCFG_MEMTYPE_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr23529Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = PeripheralNote: This register field is sticky.000x0R/WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr23537Reserved for future use.110x0RCFG_MEMTYPE_BOUNDARY_LOW_ADDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_SETDWC_pcie_wire_cpcie_usp_4x8.csr23551Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are "00". Addresses up to but not including this value are in the lower address space region; addresses equal or greater than this value are in the upper address space region.Note: This register field is sticky.3120x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFCOHERENCY_CONTROL_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr235670x1E4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFFACE Cache Coherency Control Register 2falsefalsefalsefalseCFG_MEMTYPE_BOUNDARY_HIGH_ADDRPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_SETDWC_pcie_wire_cpcie_usp_4x8.csr23566Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFCOHERENCY_CONTROL_3_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr236250x1E8R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFFACE Cache Coherency Control Register 3falsefalsefalsefalse--200x0rCFG_MSTR_ARCACHE_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr23583Master Read CACHE Signal Behavior.Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE fieldNote: This register field is sticky.630x0R/W--1070x0rCFG_MSTR_AWCACHE_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr23599Master Write CACHE Signal Behavior.Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE fieldNote: for message requests the value of mstr_awcache is always "0000" regardless of the value of this bitNote: This register field is sticky.14110x0R/W--18150x0rCFG_MSTR_ARCACHE_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr23610Master Read CACHE Signal Value.Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'.Note: This register field is sticky.22190x0R/W--26230x0rCFG_MSTR_AWCACHE_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr23624Master Write CACHE Signal Value.Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'.Note: not applicable to message requests; for message requests the value of mstr_awcache is always "0000"Note: This register field is sticky.30270x0R/W--31310x0rregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFAXI_MSTR_MSG_ADDR_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr236580x1F0R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFFLower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases, the third and fourth DWORDs of a message (Msg/MsgD) TLP header were delivered though the AXI master address bus (mstr_awaddr). These DWORDS are now supplied through the mstr_awmisc_info_hdr_34dw[63:0] output; and the value on mstr_awaddr is driven to the value you have programmed into the AXI_MSTR_MSG_ADDR_LOW_OFF and AXI_MSTR_MSG_ADDR_HIGH_OFF registers.falsefalsefalsefalseCFG_AXIMSTR_MSG_ADDR_LOW_RESERVEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SETDWC_pcie_wire_cpcie_usp_4x8.csr23647Reserved for future use.Note: This register field is sticky.1100x000RCFG_AXIMSTR_MSG_ADDR_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SETDWC_pcie_wire_cpcie_usp_4x8.csr23657Lower 20 bits of the programmable AXI address for Messages.Note: This register field is sticky.31120x00000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFAXI_MSTR_MSG_ADDR_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr236730x1F4R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFFUpper 32 bits of the programmable AXI address where Messages coming from wire are mapped to.falsefalsefalsefalseCFG_AXIMSTR_MSG_ADDR_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SETDWC_pcie_wire_cpcie_usp_4x8.csr23672Upper 32 bits of the programmable AXI address for Messages.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFPCIE_VERSION_NUMBER_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr236980x1F8R0x3533302aPE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFFPCIe Controller IIP Release Version Number. The version number is given inhex format. You should convert each pair of hex characters to ASCII to interpret.Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga**Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01GA is a general release available on www.designware.comEA is an early release available on a per-customer basis.falsefalsefalsefalseVERSION_NUMBERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr23697Version Number.3100x3533302aRregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFPCIE_VERSION_TYPE_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr237230x1FCR0x6c703038PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFFPCIe Controller IIP Release Version Type. The type is given inhex format. You should convert each pair of hex characters to ASCII to interpret.Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga**Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01GA is a general release available on www.designware.comEA is an early release available on a per-customer basis.falsefalsefalsefalseVERSION_TYPEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr23722Version Type.3100x6c703038RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFMSIX_ADDRESS_MATCH_LOW_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr237650x240R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFFMSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_HIGH_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPsfalsefalsefalsefalseMSIX_ADDRESS_MATCH_ENPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr23745MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present.Note: This register field is sticky.000x0R/WMSIX_ADDRESS_MATCH_RESERVED_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr23755Reserved.Note: This register field is sticky.110x0RMSIX_ADDRESS_MATCH_LOWPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_SETDWC_pcie_wire_cpcie_usp_4x8.csr23764MSI-X Address Match Low Address.Note: This register field is sticky.3120x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFMSIX_ADDRESS_MATCH_HIGH_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr237870x244R/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFFMSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_LOW_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPsfalsefalsefalsefalseMSIX_ADDRESS_MATCH_HIGHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_SETDWC_pcie_wire_cpcie_usp_4x8.csr23786MSI-X Address Match High Address.Note: This register field is sticky.3100x00000000R/WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFMSIX_DOORBELL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr238610x248W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSIX_DOORBELL_OFFMSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. - For AXI configurations: when your local application writes (MWr) to the address defined in MSIX_ADDRESS_MATCH_LOW_OFF, the controller will load this register with the contents of the MWr and subsequently create and send MSI-X TLPs. - For AHB configurations: the MSI-X Table RAM feature is not supported. - For non-AMBA configurations: when your local application writes to this register, the controller will create and send MSI-X TLPs.falsefalsefalsefalseMSIX_DOORBELL_VECTORPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr23812MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for.1000x000WMSIX_DOORBELL_RESERVED_11PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_SETDWC_pcie_wire_cpcie_usp_4x8.csr23819Reserved.11110x0WMSIX_DOORBELL_TCPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_SETDWC_pcie_wire_cpcie_usp_4x8.csr23828MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with.14120x0WMSIX_DOORBELL_VF_ACTIVEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_SETDWC_pcie_wire_cpcie_usp_4x8.csr23837MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction.15150x0WMSIX_DOORBELL_VFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_SETDWC_pcie_wire_cpcie_usp_4x8.csr23845MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction.23160x00WMSIX_DOORBELL_PFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_SETDWC_pcie_wire_cpcie_usp_4x8.csr23853MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction.28240x00WMSIX_DOORBELL_RESERVED_29_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr23860Reserved.31290x0WregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFMSIX_RAM_CTRL_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr239990x24CR/W0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFFMSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook.falsefalsefalsefalseMSIX_RAM_CTRL_TABLE_DSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_SETDWC_pcie_wire_cpcie_usp_4x8.csr23879MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode.Note: This register field is sticky.000x0R/WMSIX_RAM_CTRL_TABLE_SDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_SETDWC_pcie_wire_cpcie_usp_4x8.csr23890MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode.Note: This register field is sticky.110x0R/WMSIX_RAM_CTRL_RESERVED_2_7PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr23900Reserved.Note: This register field is sticky.720x00RMSIX_RAM_CTRL_PBA_DSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_SETDWC_pcie_wire_cpcie_usp_4x8.csr23911MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode.Note: This register field is sticky.880x0R/WMSIX_RAM_CTRL_PBA_SDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_SETDWC_pcie_wire_cpcie_usp_4x8.csr23922MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode.Note: This register field is sticky.990x0R/WMSIX_RAM_CTRL_RESERVED_10_15PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr23932Reserved.Note: This register field is sticky.15100x00RMSIX_RAM_CTRL_BYPASSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_SETDWC_pcie_wire_cpcie_usp_4x8.csr23948MSIX RAM Control Bypass. The bypass field, when set, disables the internal generation of low power signals for both RAMs.It is up to the application to ensure the RAMs are in the proper power state before trying to access them. Moreover, the application needs to observe all timing requirements of the RAM low power signals before trying to use the MSIX functionality.Note: This register field is sticky.16160x0R/WMSIX_RAM_CTRL_RESERVED_17_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr23958Reserved.Note: This register field is sticky.23170x00RMSIX_RAM_CTRL_DBG_TABLEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr23973MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.Note: This register field is sticky.24240x0R/WMSIX_RAM_CTRL_DBG_PBAPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_SETDWC_pcie_wire_cpcie_usp_4x8.csr23988MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.Note: This register field is sticky.25250x0R/WMSIX_RAM_CTRL_RESERVED_26_31PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr23998Reserved.Note: This register field is sticky.31260x00RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFPL_LTR_LATENCY_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr240920x430R0x00000000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFFLTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port, the register fields capture the corresponding fields in the LTR messages that are transmitted by the port. For a downstream port, the register fields capture the corresponding fields in the LTR messages that are received by the port. The full content of the register is reflected on the app_ltr_latency[31:0] output.falsefalsefalsefalseSNOOP_LATENCY_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24022Snoop Latency Value.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 900x000RSNOOP_LATENCY_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24033Snoop Latency Scale.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 12100x0RRSVDP_13PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_SETDWC_pcie_wire_cpcie_usp_4x8.csr24040Reserved for future use.14130x0RSNOOP_LATENCY_REQUIREPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24051Snoop Latency Requirement.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 15150x0RNO_SNOOP_LATENCY_VALUEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24062No Snoop Latency Value.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 25160x000RNO_SNOOP_LATENCY_SCALEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24073No Snoop Latency Scale.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 28260x0RRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr24080Reserved for future use.30290x0RNO_SNOOP_LATENCY_REQUIREPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24091No Snoop Latency Requirement.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 31310x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFAUX_CLK_FREQ_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr241270x440R/W0x00000018PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFFAuxiliary Clock Frequency Control Register.falsefalsefalsefalseAUX_CLK_FREQPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr24118The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk.Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted.If the actual frequency (f) of aux_clk does not exactly match the programmed frequency (f_prog), then there is an error in the time counted by the controller that can be expressed in percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3 MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the controller on aux_clk will be 20% greater than the time in us programmed in the corresponding time register (for example T_POWER_ON).Note: This register field is sticky.900x018R/WRSVDP_10PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_SETDWC_pcie_wire_cpcie_usp_4x8.csr24126Reserved for future use.31100x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFL1_SUBSTATES_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr241870x444R/W0x000000d2PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_L1_SUBSTATES_OFFL1 Substates Timing Register.falsefalsefalsefalseL1SUB_T_POWER_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SETDWC_pcie_wire_cpcie_usp_4x8.csr24140Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3.Note: This register field is sticky.100x2R/WL1SUB_T_L1_2PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr24150Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15.Note: This register field is sticky.520x4R/WL1SUB_T_PCLKACKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_SETDWC_pcie_wire_cpcie_usp_4x8.csr24163Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be L1SUB_T_PCLKACK + 1. Range is 0..3Note: This register field is sticky.760x3R/WL1SUB_LOW_POWER_CLOCK_SWITCH_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24178If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the controller will delay the switching of aux_clk to the slow platform clock until it detects that the link partner has de-asserted CLKREQ#.Note: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr24186Reserved for future use.3190x000000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFPOWERDOWN_CTRL_STATUS_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr242480x448R/W0x00000220PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFFPowerdown Control and Status Register.falsefalsefalsefalsePOWERDOWN_FORCEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24206This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event that the P2 Powerdown transition does not complete. It will allow the controller to proceed with the transition to the P1 Powerdown state. This field always reads back as 1'b0.000x0WRSVDP_1PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr24214Reserved for future use.310x0RPOWERDOWN_MAC_POWERDOWNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_SETDWC_pcie_wire_cpcie_usp_4x8.csr24225This field represents the Powerdown value driven by the controller to the PHY.740x2RPOWERDOWN_PHY_POWERDOWNPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_SETDWC_pcie_wire_cpcie_usp_4x8.csr24239This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller, when the PHY has returned the Phystatus acknowledgment for the Powerdown transition.1180x2RRSVDP_12PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr24247Reserved for future use.31120x00000RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFGEN4_LANE_MARGINING_1_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr243360x480R/W0x05201409PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFFGen4 Lane Margining 1 Register.falsefalsefalsefalseMARGINING_NUM_TIMING_STEPSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_SETDWC_pcie_wire_cpcie_usp_4x8.csr24264M(NumTimingSteps) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.500x09R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr24272Reserved for future use.760x0RMARGINING_MAX_TIMING_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr24285M(MaxTimingOffset) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.1380x14R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr24293Reserved for future use.15140x0RMARGINING_NUM_VOLTAGE_STEPSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_SETDWC_pcie_wire_cpcie_usp_4x8.csr24306M(NumVoltageSteps) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.22160x20R/WRSVDP_23PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr24314Reserved for future use.23230x0RMARGINING_MAX_VOLTAGE_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr24327M(MaxVoltageOffset) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.29240x05R/WRSVDP_30PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_SETDWC_pcie_wire_cpcie_usp_4x8.csr24335Reserved for future use.31300x0RregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFGEN4_LANE_MARGINING_2_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr244830x484R/W0x060f0000PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFFGen4 Lane Margining 2 Register.falsefalsefalsefalseMARGINING_SAMPLE_RATE_VOLTAGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24355M(SamplingRateVoltage) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The M(SamplingRateVoltage) is fixed to 63 internally.Note: This register field is sticky.500x00R/WRSVDP_6PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr24363Reserved for future use.760x0RMARGINING_SAMPLE_RATE_TIMINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_SETDWC_pcie_wire_cpcie_usp_4x8.csr24379M(SamplingRateTiming) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter , see the PCI Express Base Specification 4.0.Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The M(SamplingRateTiming) is fixed to 63 internally.Note: This register field is sticky.1380x00R/WRSVDP_14PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr24387Reserved for future use.15140x0RMARGINING_MAXLANESPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_SETDWC_pcie_wire_cpcie_usp_4x8.csr24400M(MaxLanes) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.20160x0fR/WRSVDP_21PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_SETDWC_pcie_wire_cpcie_usp_4x8.csr24408Reserved for future use.23210x0RMARGINING_VOLTAGE_SUPPORTEDPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr24421M(VoltageSupported) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.24240x0R/WMARGINING_IND_UP_DOWN_VOLTAGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24434M(IndUpDownVoltage) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.25250x1R/WMARGINING_IND_LEFT_RIGHT_TIMINGPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_SETDWC_pcie_wire_cpcie_usp_4x8.csr24447M(IndLeftRightTiming) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.26260x1R/WMARGINING_SAMPLE_REPORTING_METHODPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_SETDWC_pcie_wire_cpcie_usp_4x8.csr24461M(SampleReportingMethod) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.27270x0R/WMARGINING_IND_ERROR_SAMPLERPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_SETDWC_pcie_wire_cpcie_usp_4x8.csr24474M(IndErrorSampler) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.28280x0R/WRSVDP_29PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr24482Reserved for future use.30290x0R--31310x0rregisterPE0_DWC_pcie_ctl_AXI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFPIPE_RELATED_OFFPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_BYTE_ADDRESSPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_OFFSETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr245450x490R/W0x00000022PE0_DWC_pcie_ctl_AXI_Slave_PF0_PORT_LOGIC_PIPE_RELATED_OFFPIPE Related Register.This register controls the pipe's capabitity, control, and status parameters.falsefalsefalsefalseRX_MESSAGE_BUS_WRITE_BUFFER_DEPTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr24503RXMessageBusWriteBufferDepth defined in the PIPE Specification.Indicates the number of write buffer entries that the PHY has implemented to receive writes from the controller.If the value is less than 2 for PIPE 5.1.1 or 1 for PIPE 4.4.1, the controller issues only write_commited commands, never write_uncommitted.Note: This register field is sticky.300x2R/WTX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr24517TXMessageBusMinWriteBufferDepth defined in the PIPE Specification.Indicates the minimum number of write buffer entries that the PHY expects the controller to implement to receive writes from it.Note: This register field is sticky.740x2RPIPE_GARBAGE_DATA_MODEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24536PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received after the electrical idle ordered-set until when any of the following three conditions are true: -- RxValid is deasserted -- a valid RxStartBlock is received at 128b/130b encoding -- a valid COM symbol is received at 8b/10b encodingNote: This register field is sticky.880x0R/WRSVDP_9PE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_WIDTHPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_MSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_LSBPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_RANGEPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_RESETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_FIELD_MASKPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_GETPE0_DWC_PCIE_CTL_AXI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr24544Reserved for future use.3190x000000RDBI_SlaveaddressmapDBI_SlaveDBI_SlaveDWC_pcie_wire_cpcie_usp_4x8.csr49077R/WDBI_SlaveDWC PCIE-EP Memory MapgroupDBI_Slave.PF0_TYPE0_HDRgroupDBI_Slave.PF0_PM_CAPgroupDBI_Slave.PF0_MSI_CAPgroupDBI_Slave.PF0_PCIE_CAPgroupDBI_Slave.PF0_MSIX_CAPgroupDBI_Slave.PF0_AER_CAPgroupDBI_Slave.PF0_VC_CAPgroupDBI_Slave.PF0_SPCIE_CAPgroupDBI_Slave.PF0_PL16G_CAPgroupDBI_Slave.PF0_MARGIN_CAPgroupDBI_Slave.PF0_TPH_CAPgroupDBI_Slave.PF0_LTR_CAPgroupDBI_Slave.PF0_L1SUB_CAPgroupDBI_Slave.PF0_LNR_CAPgroupDBI_Slave.PF0_RAS_DES_CAPgroupDBI_Slave.PF0_VSECRAS_CAPgroupDBI_Slave.PF0_DLINK_CAPgroupDBI_Slave.PF0_RESBAR_CAPgroupDBI_Slave.PF0_VF_RESBAR_CAPgroupDBI_Slave.PF0_PORT_LOGIC0x00xCFFDBI_SlaveDBI_Slave0x00x3FDBI_Slave.PF0_TYPE0_HDRDBI_Slave.PF0_TYPE0_HDR0x00x0DBI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REGDBI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REG0x40x4DBI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REGDBI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REG0x80x8DBI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_IDDBI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_ID0xC0xCDBI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGDBI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG0x100x10DBI_Slave.PF0_TYPE0_HDR.BAR0_REGDBI_Slave.PF0_TYPE0_HDR.BAR0_REG0x140x14DBI_Slave.PF0_TYPE0_HDR.BAR1_REGDBI_Slave.PF0_TYPE0_HDR.BAR1_REG0x180x18DBI_Slave.PF0_TYPE0_HDR.BAR2_REGDBI_Slave.PF0_TYPE0_HDR.BAR2_REG0x1C0x1CDBI_Slave.PF0_TYPE0_HDR.BAR3_REGDBI_Slave.PF0_TYPE0_HDR.BAR3_REG0x200x20DBI_Slave.PF0_TYPE0_HDR.BAR4_REGDBI_Slave.PF0_TYPE0_HDR.BAR4_REG0x240x24DBI_Slave.PF0_TYPE0_HDR.BAR5_REGDBI_Slave.PF0_TYPE0_HDR.BAR5_REG0x280x28DBI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REGDBI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REG0x2C0x2CDBI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGDBI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG0x300x30DBI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REGDBI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REG0x340x34DBI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REGDBI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REG0x380x3B0x3C0x3CDBI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGDBI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG0x400x47DBI_Slave.PF0_PM_CAPDBI_Slave.PF0_PM_CAP0x400x40DBI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGDBI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REG0x440x44DBI_Slave.PF0_PM_CAP.CON_STATUS_REGDBI_Slave.PF0_PM_CAP.CON_STATUS_REG0x480x4F0x500x67DBI_Slave.PF0_MSI_CAPDBI_Slave.PF0_MSI_CAP0x500x50DBI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGDBI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REG0x540x54DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REG0x580x58DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REG0x5C0x5CDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REG0x600x60DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REG0x640x64DBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REG0x680x6F0x700xABDBI_Slave.PF0_PCIE_CAPDBI_Slave.PF0_PCIE_CAP0x700x70DBI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGDBI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG0x740x74DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGDBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REG0x780x78DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSDBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUS0x7C0x7CDBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGDBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REG0x800x80DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGDBI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REG0x840x930x940x94DBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGDBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REG0x980x98DBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGDBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REG0x9C0x9CDBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGDBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REG0xA00xA0DBI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGDBI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REG0xA40xAB0xAC0xAF0xB00xBCDBI_Slave.PF0_MSIX_CAPDBI_Slave.PF0_MSIX_CAP0xB00xB0DBI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGDBI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REG0xB40xB4DBI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGDBI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REG0xB80xB8DBI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGDBI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REG0xBC0xBC0xBD0xFF0x1000x147DBI_Slave.PF0_AER_CAPDBI_Slave.PF0_AER_CAP0x1000x100DBI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFDBI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFF0x1040x104DBI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFDBI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFF0x1080x108DBI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFDBI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFF0x10C0x10CDBI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFDBI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFF0x1100x110DBI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFDBI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFF0x1140x114DBI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFDBI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFF0x1180x118DBI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFDBI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFF0x11C0x11CDBI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFDBI_Slave.PF0_AER_CAP.HDR_LOG_0_OFF0x1200x120DBI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFDBI_Slave.PF0_AER_CAP.HDR_LOG_1_OFF0x1240x124DBI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFDBI_Slave.PF0_AER_CAP.HDR_LOG_2_OFF0x1280x128DBI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFDBI_Slave.PF0_AER_CAP.HDR_LOG_3_OFF0x12C0x1370x1380x138DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFF0x13C0x13CDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFF0x1400x140DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFF0x1440x144DBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFF0x1480x197DBI_Slave.PF0_VC_CAPDBI_Slave.PF0_VC_CAP0x1480x148DBI_Slave.PF0_VC_CAP.VC_BASEDBI_Slave.PF0_VC_CAP.VC_BASE0x14C0x14CDBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_10x1500x150DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2DBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_20x1540x154DBI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGDBI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REG0x1580x158DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC00x15C0x15CDBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC00x1600x160DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC00x1640x164DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC10x1680x168DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC10x16C0x16CDBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC10x1700x170DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC20x1740x174DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC20x1780x178DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC20x17C0x17CDBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3DBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC30x1800x180DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3DBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC30x1840x184DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3DBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC30x1880x1970x1980x1B7DBI_Slave.PF0_SPCIE_CAPDBI_Slave.PF0_SPCIE_CAP0x1980x198DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REG0x19C0x19CDBI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGDBI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REG0x1A00x1A0DBI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGDBI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REG0x1A40x1A4DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REG0x1A80x1A8DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REG0x1AC0x1ACDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REG0x1B00x1B0DBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REG0x1B40x1B70x1B80x1DFDBI_Slave.PF0_PL16G_CAPDBI_Slave.PF0_PL16G_CAP0x1B80x1B8DBI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGDBI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REG0x1BC0x1BCDBI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGDBI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REG0x1C00x1C0DBI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGDBI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REG0x1C40x1C4DBI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGDBI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REG0x1C80x1C8DBI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGDBI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REG0x1CC0x1CCDBI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGDBI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REG0x1D00x1D0DBI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGDBI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REG0x1D40x1D70x1D80x1D8DBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGDBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REG0x1DC0x1DCDBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGDBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REG0x1E00x207DBI_Slave.PF0_MARGIN_CAPDBI_Slave.PF0_MARGIN_CAP0x1E00x1E0DBI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGDBI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REG0x1E40x1E4DBI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGDBI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REG0x1E80x1E8DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REG0x1EC0x1ECDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REG0x1F00x1F0DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REG0x1F40x1F4DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REG0x1F80x1F8DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REG0x1FC0x1FCDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REG0x2000x200DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REG0x2040x204DBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REG0x2080x293DBI_Slave.PF0_TPH_CAPDBI_Slave.PF0_TPH_CAP0x2080x208DBI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGDBI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REG0x20C0x20CDBI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGDBI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REG0x2100x210DBI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGDBI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REG0x2140x214DBI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0DBI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_00x2180x2930x2940x29BDBI_Slave.PF0_LTR_CAPDBI_Slave.PF0_LTR_CAP0x2940x294DBI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REGDBI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REG0x2980x298DBI_Slave.PF0_LTR_CAP.LTR_LATENCY_REGDBI_Slave.PF0_LTR_CAP.LTR_LATENCY_REG0x29C0x2ABDBI_Slave.PF0_L1SUB_CAPDBI_Slave.PF0_L1SUB_CAP0x29C0x29CDBI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGDBI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REG0x2A00x2A0DBI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGDBI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REG0x2A40x2A4DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGDBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REG0x2A80x2A8DBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGDBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REG0x2AC0x2BB0x2BC0x2C3DBI_Slave.PF0_LNR_CAPDBI_Slave.PF0_LNR_CAP0x2BC0x2BCDBI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFFDBI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFF0x2C00x2C0DBI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFFDBI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFF0x2C40x3C3DBI_Slave.PF0_RAS_DES_CAPDBI_Slave.PF0_RAS_DES_CAP0x2C40x2C4DBI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGDBI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REG0x2C80x2C8DBI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGDBI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REG0x2CC0x2CCDBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGDBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REG0x2D00x2D0DBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGDBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REG0x2D40x2D4DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGDBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REG0x2D80x2D8DBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGDBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REG0x2DC0x2DCDBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGDBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REG0x2E00x2F30x2F40x2F4DBI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REG0x2F80x2F8DBI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REG0x2FC0x2FCDBI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REG0x3000x300DBI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REG0x3040x304DBI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REG0x3080x308DBI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REG0x30C0x30CDBI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REG0x3100x310DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REG0x3140x314DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REG0x3180x318DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REG0x31C0x31CDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REG0x3200x320DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REG0x3240x324DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REG0x3280x328DBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REG0x32C0x32CDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REG0x3300x330DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REG0x3340x334DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REG0x3380x338DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REG0x33C0x33CDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REG0x3400x340DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REG0x3440x344DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REG0x3480x348DBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REG0x34C0x34CDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REG0x3500x350DBI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGDBI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REG0x3540x3630x3640x364DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGDBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REG0x3680x368DBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGDBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REG0x36C0x3730x3740x374DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REG0x3780x378DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REG0x37C0x37CDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REG0x3800x380DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REG0x3840x384DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REG0x3880x388DBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REG0x38C0x3930x3940x394DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REG0x3980x398DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REG0x39C0x39CDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REG0x3A00x3A30x3A40x3A4DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REG0x3A80x3A8DBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REG0x3AC0x3ACDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REG0x3B00x3C30x3C40x3FBDBI_Slave.PF0_VSECRAS_CAPDBI_Slave.PF0_VSECRAS_CAP0x3C40x3C4DBI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFF0x3C80x3C8DBI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFF0x3CC0x3CCDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFF0x3D00x3D0DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFF0x3D40x3D4DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFF0x3D80x3D8DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFF0x3DC0x3DCDBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFF0x3E00x3E0DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFF0x3E40x3E4DBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFF0x3E80x3E8DBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFF0x3EC0x3ECDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFF0x3F00x3F0DBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFF0x3F40x3F4DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFF0x3F80x3F8DBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFDBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFF0x3FC0x407DBI_Slave.PF0_DLINK_CAPDBI_Slave.PF0_DLINK_CAP0x3FC0x3FCDBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFDBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFF0x4000x400DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFDBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFF0x4040x404DBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFDBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFF0x4080x43BDBI_Slave.PF0_RESBAR_CAPDBI_Slave.PF0_RESBAR_CAP0x4080x408DBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REGDBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REG0x40C0x40CDBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REGDBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REG0x4100x410DBI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REGDBI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REG0x4140x43B0x43C0x4470x4480x47BDBI_Slave.PF0_VF_RESBAR_CAPDBI_Slave.PF0_VF_RESBAR_CAP0x4480x448DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REGDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REG0x44C0x44CDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REGDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REG0x4500x450DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REGDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REG0x4540x454DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REGDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REG0x4580x458DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REGDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REG0x45C0x45CDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REGDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REG0x4600x460DBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REGDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REG0x4640x47B0x47C0x6FF0x7000xCFFDBI_Slave.PF0_PORT_LOGICDBI_Slave.PF0_PORT_LOGIC0x7000x700DBI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFDBI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFF0x7040x704DBI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFDBI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFF0x7080x708DBI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFDBI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFF0x70C0x70CDBI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFF0x7100x710DBI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFF0x7140x714DBI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFDBI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFF0x7180x718DBI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFDBI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFF0x71C0x71CDBI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFDBI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFF0x7200x720DBI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFDBI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFF0x7240x724DBI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF0x7280x728DBI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFDBI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFF0x72C0x72CDBI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFDBI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFF0x7300x730DBI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFF0x7340x734DBI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFF0x7380x738DBI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFF0x73C0x73CDBI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFF0x7400x740DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFDBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFF0x7440x744DBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFDBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFF0x7480x748DBI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFF0x74C0x74CDBI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFF0x7500x750DBI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFF0x7540x754DBI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFF0x7580x758DBI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFF0x75C0x75CDBI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFF0x7600x760DBI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFF0x7640x764DBI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFF0x7680x768DBI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFF0x76C0x76CDBI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFF0x7700x770DBI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFF0x7740x774DBI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFF0x7780x80B0x80C0x80CDBI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFF0x8100x810DBI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFF0x8140x814DBI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFDBI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFF0x8180x81B0x81C0x81CDBI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFF0x8200x820DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFF0x8240x824DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFF0x8280x828DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFF0x82C0x82CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFF0x8300x830DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFF0x8340x834DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFF0x8380x838DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFF0x83C0x83CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFF0x8400x840DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFF0x8440x844DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFF0x8480x848DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFF0x84C0x84CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFF0x8500x850DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFF0x8540x854DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFF0x8580x858DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFF0x85C0x85CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFF0x8600x860DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFF0x8640x864DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFF0x8680x868DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFF0x86C0x86CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFF0x8700x870DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFF0x8740x874DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFF0x8780x878DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFF0x87C0x87CDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFF0x8800x880DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFF0x8840x884DBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFF0x8880x888DBI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFDBI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFF0x88C0x88CDBI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFF0x8900x890DBI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFDBI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFF0x8940x8A70x8A80x8A8DBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFDBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFF0x8AC0x8ACDBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFDBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFF0x8B00x8B30x8B40x8B4DBI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFF0x8B80x8B8DBI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFDBI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFF0x8BC0x8BCDBI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFDBI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFF0x8C00x8C0DBI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFDBI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFF0x8C40x8C4DBI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFF0x8C80x8C8DBI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFDBI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFF0x8CC0x8CCDBI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFDBI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFF0x8D00x8D0DBI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFDBI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFF0x8D40x8D4DBI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFDBI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFF0x8D80x8D8DBI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFF0x8DC0x8DF0x8E00x8E0DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFDBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFF0x8E40x8E4DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFDBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFF0x8E80x8E8DBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFDBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFF0x8EC0x8EF0x8F00x8F0DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFDBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFF0x8F40x8F4DBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFDBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFF0x8F80x8F8DBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFDBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFF0x8FC0x8FCDBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFDBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFF0x9000x93F0x9400x940DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFDBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFF0x9440x944DBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFDBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFF0x9480x948DBI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFDBI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFF0x94C0x94CDBI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFDBI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFF0x9500xB2F0xB300xB30DBI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFDBI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFF0xB340xB3F0xB400xB40DBI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFDBI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFF0xB440xB44DBI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFDBI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFF0xB480xB48DBI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFDBI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFF0xB4C0xB7F0xB800xB80DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFDBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFF0xB840xB84DBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFDBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFF0xB880xB8F0xB900xB90DBI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFDBI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFF0xB940xCFFgroupDBI_Slave.PF0_TYPE0_HDRPF0_TYPE0_HDRDBI_SLAVE_PF0_TYPE0_HDR_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr259380x0R/WDBI_Slave_PF0_TYPE0_HDRPF PCI-Compatible Configuration Space Header Type0registerDBI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REGregisterDBI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REGregisterDBI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_IDregisterDBI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGregisterDBI_Slave.PF0_TYPE0_HDR.BAR0_REGregisterDBI_Slave.PF0_TYPE0_HDR.BAR1_REGregisterDBI_Slave.PF0_TYPE0_HDR.BAR2_REGregisterDBI_Slave.PF0_TYPE0_HDR.BAR3_REGregisterDBI_Slave.PF0_TYPE0_HDR.BAR4_REGregisterDBI_Slave.PF0_TYPE0_HDR.BAR5_REGregisterDBI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REGregisterDBI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGregisterDBI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REGregisterDBI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REGregisterDBI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGregisterDBI_Slave.PF0_TYPE0_HDR.DEVICE_ID_VENDOR_ID_REGDEVICE_ID_VENDOR_ID_REGDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr245960x0R0xeb011e0aDBI_Slave_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REGDevice ID and Vendor ID Register.falsefalsefalsefalsePCI_TYPE0_VENDOR_IDDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_MSBDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_LSBDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_RANGEDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_RESETDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_GETDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr24579Vendor ID.The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh, which is an invalid value for Vendor ID.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x1e0aRPCI_TYPE0_DEVICE_IDDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_MSBDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_LSBDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_RANGEDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_RESETDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_GETDBI_SLAVE_PF0_TYPE0_HDR_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr24595Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31160xeb01RregisterDBI_Slave.PF0_TYPE0_HDR.STATUS_COMMAND_REGSTATUS_COMMAND_REGDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr249320x4R/W0x00100000DBI_Slave_PF0_TYPE0_HDR_STATUS_COMMAND_REGStatus and Command Register.falsefalsefalsefalsePCI_TYPE0_IO_ENDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr24618IO Space Enable.Controls a Function's response to I/O Space accesses. - When this bit is set, the Function is enabled to decode the address and further process I/O Space accesses. - When this bit is clear, all received I/O accesses are caused to be handled as Unsupported Requests.For a Function that does not support I/O Space accesses, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: !has_io_bar ? RO : RW - Dbi: !has_io_bar ? RO : RW 000x0R/WPCI_TYPE0_MEM_SPACE_ENDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr24637Memory Space Enable.Controls a Function's response to Memory Space accesses. - When this bit is set, the Function is enabled to decode the address and further process Memory Space accesses. - When this bit is clear, all received Memory Space accesses are caused to be handled as Unsupported Requests.For a Function does not support Memory Space accesses, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: !has_mem_bar ? RO : RW - Dbi: !has_mem_bar ? RO : RW 110x0R/WPCI_TYPE0_BUS_MASTER_ENDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr24660Bus Master Enable.Controls the ability of a Function to issue Memory and I/O Read/Write requests. - When this bit is set, the Function is allowed to issue Memory or I/O Requests. - When this bit is clear, the Function is not allowed to issue any Memory or I/O Requests.Requests other than Memory or I/O Requests are not controlled by this bit.Note: MSI/MSI-X interrupt Messages are in-band memory writes, setting the Bus Master Enable bit to 0b disables MSI/MSI-X interrupt Messages as well.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 220x0R/WPCI_TYPE0_SPECIAL_CYCLE_OPERATIONDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_SETDWC_pcie_wire_cpcie_usp_4x8.csr24671Special Cycle Enable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.330x0RPCI_TYPE_MWI_ENABLEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24684Memory Write and Invalidate.This bit was originally described in the PCI Local Bus Specification and thePCI-to-PCI Bridge architecture specification. Its functionality does not applyto PCI Express, the controller hardwires this bit to 0b.440x0RPCI_TYPE_VGA_PALETTE_SNOOPDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_SETDWC_pcie_wire_cpcie_usp_4x8.csr24696VGA Palette Snoop.This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge architecture specification. Its functionality does not apply to PCI Express, the controller hardwires this bit to 0b.550x0RPCI_TYPE0_PARITY_ERR_ENDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr24708Parity Error Response.This bit controls the logging of poisoned TLPs in the Master Data Parity Errorbit in the Status register. For more details see the "Error Registers" section of the PCI Express Base Specification.660x0R/WPCI_TYPE_IDSEL_STEPPINGDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_SETDWC_pcie_wire_cpcie_usp_4x8.csr24719IDSEL Stepping/Wait Cycle Control.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.770x0RPCI_TYPE0_SERRENDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_SETDWC_pcie_wire_cpcie_usp_4x8.csr24735SERR# Enable.When set, this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function.Note: The errors are reported if enabled either through this bit orthrough the PCI Express specific bits in the Device Control register. For moredetails see the "Error Registers" section of the PCI Express Base Specification.880x0R/WRSVDP_9DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr24743Reserved for future use.990x0RPCI_TYPE0_INT_ENDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr24765Interrupt Disable.Controls the ability of a Function to generate INTx emulation interrupts. - When set, Functions are prevented from asserting INTx interrupts.Note: - Any INTx emulation interrupts already asserted by the Function must be deasserted when this bit is Set. INTx interrupts use virtual wires that must, if asserted, be deasserted using the appropriate Deassert_INTx message(s) when this bit is set. - Only the INTx virtual wire interrupt(s) associated with the Function(s) for which this bit is set are affected. - For functions that generate INTx interrupts, this bit is required. For functions that do not generate INTx interrupts, this bit is optional.10100x0R/WPCI_TYPE_RESERVDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_PCI_TYPE_RESERV_SETDWC_pcie_wire_cpcie_usp_4x8.csr24774Reserved.15110x00R--16160x0rRSVDP_17DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_17_SETDWC_pcie_wire_cpcie_usp_4x8.csr24782Reserved for future use.18170x0RINT_STATUSDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_INT_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr24796Emulation interrupt pending.When set, indicates that an INTx emulation interrupt is pending internally in the Function. Setting the Interrupt Disable bit has no effect on the state of this bit. For Functions that do not generate INTx interrupts, the controller hardwires this bit to 0b.1919RCAP_LISTDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_CAP_LIST_SETDWC_pcie_wire_cpcie_usp_4x8.csr24808Capabilities List.Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure, the controller hardwires this bit to 1b.20200x1RFAST_66MHZ_CAPDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr2481966MHz Capable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.21210x0RRSVDP_22DBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr24827Reserved for future use.22220x0RFAST_B2B_CAPDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_FAST_B2B_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr24838Fast Back to Back Transaction Capable.This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.23230x0RMASTER_DPEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_MASTER_DPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24854Master Data Parity Error.This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Function receives a Poisoned Completion - Function transmits a Poisoned RequestIf the Parity Error Response bit is 0b, this bit is never set.24240x0R/W1CDEV_SEL_TIMINGDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DEV_SEL_TIMING_SETDWC_pcie_wire_cpcie_usp_4x8.csr24865DEVSEL Timing.This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this field to 00b.26250x0RSIGNALED_TARGET_ABORTDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr24878Signaled Target Abort.This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. The controller hardwires this bit to 0b for Functions that do not signal Completer Abort.27270x0R/W1CRCVD_TARGET_ABORTDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr24891Received Target Abort.This bit is set when a Requester receives a Completion with Completer Abort Completion Status. For Functions that do not make Non-Posted Requests on their own behalf, the controller hardwires this bit to 0b.28280x0R/W1CRCVD_MASTER_ABORTDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr24905Received Master Abort.This bit is set when a Requester receives a Completion with Unsupported Request Completion Status. For Functions that do not make Non-Posted Requests on their own behalf, the controller hardwires this bit to 0b.29290x0R/W1CSIGNALED_SYS_ERRDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_SETDWC_pcie_wire_cpcie_usp_4x8.csr24919Signaled System Error.This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL message, and the SERR# Enable bit in the Command register is 1b. For Functions that do not send ERR_FATAL or ERR_NONFATAL messages, the controller hardwires this bit to 0b.30300x0R/W1CDETECTED_PARITY_ERRDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_MSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_LSBDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_RANGEDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_RESETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_GETDBI_SLAVE_PF0_TYPE0_HDR_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_SETDWC_pcie_wire_cpcie_usp_4x8.csr24931Detected Parity Error.This bit is set by a Function whenever it receives a Poisoned TLP, regardless of the state the Parity Error Response bit in the Command register.31310x0R/W1CregisterDBI_Slave.PF0_TYPE0_HDR.CLASS_CODE_REVISION_IDCLASS_CODE_REVISION_IDDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr250130x8R0x00000001DBI_Slave_PF0_TYPE0_HDR_CLASS_CODE_REVISION_IDClass Code and Revision ID Register.falsefalsefalsefalseREVISION_IDDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_MSBDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_LSBDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_RANGEDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_RESETDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_GETDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_REVISION_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr24954Revision ID.The value in this register specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.700x01RPROGRAM_INTERFACEDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_MSBDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_LSBDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_RESETDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_GETDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24974Programming Interface.This field identifies a specific register-level programming interface (if any) so that device independent software can interact with the Function.Encodings for interface are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1580x00RSUBCLASS_CODEDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_MSBDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_LSBDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_RESETDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_GETDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr24993Sub-Class Code.Specifies a base class sub-class, which identifies more specifically the operation of the Function.Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23160x00RBASE_CLASS_CODEDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_MSBDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_LSBDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_RESETDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_GETDBI_SLAVE_PF0_TYPE0_HDR_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr25012Base Class Code.A code that broadly classifies the type of operation the Function performs.Encodings for base class, are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are Reserved.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31240x00RregisterDBI_Slave.PF0_TYPE0_HDR.BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGBIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr251150xCR/W0x00000000DBI_Slave_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REGBIST, Header Type, Latency Timer, and Cache Line Size Register.falsefalsefalsefalseCACHE_LINE_SIZEDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MSBDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_LSBDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_RESETDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_GETDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr25033Cache Line Size.The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However, legacy conventional PCI software may not always be able to program this register correctly especially in the case of Hot-Plug devices. This read-write register is implemented for legacy compatibility purposes but has no effect on any PCI Express devicebehavior.700x00R/WLATENCY_MASTER_TIMERDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MSBDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_LSBDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_RESETDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_GETDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SETDWC_pcie_wire_cpcie_usp_4x8.csr25046Latency Timer.The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this register to 00h.1580x00RHEADER_TYPEDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_MSBDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_LSBDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_RESETDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_GETDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr25057Header Layout.This field identifies the layout of the second part of the predefined header.The controller uses 000 0000b encoding.22160x00RMULTI_FUNCDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_MSBDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_LSBDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_RESETDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_GETDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_SETDWC_pcie_wire_cpcie_usp_4x8.csr25081Multi-Function Device. - When set, indicates that the Device may contain multiple Functions, but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear, software must not probe for Functions other than Function 0 unless explicitly indicated by another mechanism, such as an ARI or SR-IOV Capability structure.Except where stated otherwise, it is recommended that this bit be set if there are multiple Functions, and clear if there is only one Function.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RBISTDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_MSBDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_LSBDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_RESETDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_GETDBI_SLAVE_PF0_TYPE0_HDR_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_SETDWC_pcie_wire_cpcie_usp_4x8.csr25114BIST.This register is used for control and status of BIST. For Functions that do not support BIST the controller hardwires the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link.Bit descriptions: - [31]: BIST Capable.When Set, this bit indicates that the Function supports BIST. When Clear, the Function does not support BIST. - [30]: Start BIST.If BIST Capable is Set, Set this bit to invoke BIST. The Function resets the bit when BIST is complete. Software is permitted to fail the device if this bit is not Clear (BIST is not complete) 2 seconds after it had been Set. Writing this bit to 0b has no effect. This bit must be hardwired to 0b if BIST Capable is Clear. - [29:28]: Reserved. - [27:24]: Completion Code.This field encodes the status of the most recent test. A value of 0000b means that the Function has passed its test. Non-zero values mean the Function failed. Function-specific failure codes can be encoded in the non-zero values. This field's value is only meaningful when BIST Capable is Set and Start BIST is Clear. This field must be hardwired to 0000b if BIST Capable is clear.31240x00RregisterDBI_Slave.PF0_TYPE0_HDR.BAR0_REGBAR0_REGDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr252180x10R/W0x00000004DBI_Slave_PF0_TYPE0_HDR_BAR0_REGBAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR0_MEM_IODBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_MEM_IO_SETDWC_pcie_wire_cpcie_usp_4x8.csr25150BAR0 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR0_TYPEDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr25178BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR0_PREFETCHDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_PREFETCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr25200BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR0_STARTDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR0_REG_BAR0_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr25217BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterDBI_Slave.PF0_TYPE0_HDR.BAR1_REGBAR1_REGDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr253150x14R/W0x00000000DBI_Slave_PF0_TYPE0_HDR_BAR1_REGBAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR1_MEM_IODBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_MEM_IO_SETDWC_pcie_wire_cpcie_usp_4x8.csr25251BAR1 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR1_TYPEDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr25277BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR1_PREFETCHDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_PREFETCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr25297BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR1_STARTDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR1_REG_BAR1_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr25314BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterDBI_Slave.PF0_TYPE0_HDR.BAR2_REGBAR2_REGDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr254180x18R/W0x00000004DBI_Slave_PF0_TYPE0_HDR_BAR2_REGBAR2 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR2_MEM_IODBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_MEM_IO_SETDWC_pcie_wire_cpcie_usp_4x8.csr25350BAR2 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR2_TYPEDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr25378BAR2 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR2_PREFETCHDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_PREFETCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr25400BAR2 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR2_STARTDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR2_REG_BAR2_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr25417BAR2 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterDBI_Slave.PF0_TYPE0_HDR.BAR3_REGBAR3_REGDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr255150x1CR/W0x00000000DBI_Slave_PF0_TYPE0_HDR_BAR3_REGBAR3 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR3_MEM_IODBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_MEM_IO_SETDWC_pcie_wire_cpcie_usp_4x8.csr25451BAR3 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR3_TYPEDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr25477BAR3 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR3_PREFETCHDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_PREFETCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr25497BAR3 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR3_STARTDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR3_REG_BAR3_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr25514BAR3 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterDBI_Slave.PF0_TYPE0_HDR.BAR4_REGBAR4_REGDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr256180x20R/W0x00000004DBI_Slave_PF0_TYPE0_HDR_BAR4_REGBAR4 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR4_MEM_IODBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_MEM_IO_SETDWC_pcie_wire_cpcie_usp_4x8.csr25550BAR4 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0RBAR4_TYPEDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr25578BAR4 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x2RBAR4_PREFETCHDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_PREFETCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr25600BAR4 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0RBAR4_STARTDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR4_REG_BAR4_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr25617BAR4 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterDBI_Slave.PF0_TYPE0_HDR.BAR5_REGBAR5_REGDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr257150x24R/W0x00000000DBI_Slave_PF0_TYPE0_HDR_BAR5_REGBAR5 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM).falsefalsefalsefalseBAR5_MEM_IODBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_MEM_IO_SETDWC_pcie_wire_cpcie_usp_4x8.csr25651BAR5 Memory Space Indicator.This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b.Base Address registers that map to I/O Space must return a 1b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.000x0R/WBAR5_TYPEDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr25677BAR5 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space).The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. -- 01: Reserved. -- 10: Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. -- 11: Reserved. - IO Space: Bit 1 is reserved and must return 0b on reads. Bits[31:2] are used to map the function into IO space.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.210x0R/WBAR5_PREFETCHDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_PREFETCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr25697BAR5 Prefetchable. - Memory Space: Set to one if data is pre-fetchable.A Function is permitted to mark a range as prefetchable. If there are no side effects on reads, the function returns all bytes on reads regardless of the byte enables, and host bridges can merge processor writes into this range without causing errors. Bit must me clear otherwise. - IO Space: Not applicableNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R(Sticky)/W(Sticky) else R(Sticky)) else RO(Sticky) Note: This register field is sticky.330x0R/WBAR5_STARTDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_MSBDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_LSBDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_RANGEDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_RESETDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_GETDBI_SLAVE_PF0_TYPE0_HDR_BAR5_REG_BAR5_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr25714BAR5 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base.Address. Note: The access attributes of this field are as follows: - Wire: R(Sticky)/W(Sticky) if enabled else R(Sticky) - Dbi: R(Sticky)/W(Sticky) if enabled else R(Sticky) Note: This register field is sticky.3140x0000000R/WregisterDBI_Slave.PF0_TYPE0_HDR.CARDBUS_CIS_PTR_REGCARDBUS_CIS_PTR_REGDBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr257360x28R0x00000000DBI_Slave_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REGCardBus CIS Pointer Register.falsefalsefalsefalseCARDBUS_CIS_POINTERDBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_MSBDBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_LSBDBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_RANGEDBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_RESETDBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_GETDBI_SLAVE_PF0_TYPE0_HDR_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr25735CardBus CIS Pointer.Its functionality does not apply to PCI Express. It must be hardwired to 0000 0000h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.3100x00000000RregisterDBI_Slave.PF0_TYPE0_HDR.SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGSUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr257800x2CR0x00000000DBI_Slave_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REGSubsystem ID and Subsystem Vendor ID Register.These registers are used to uniquely identify the add-in card or subsystem where the PCI Express component resides. They provide a mechanism for vendors to distinguish their products from one another even though the assemblies may have the same PCI Express component on them (and, therefore, the same Vendor ID and Device ID).falsefalsefalsefalseSUBSYS_VENDOR_IDDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_MSBDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_LSBDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_RANGEDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_RESETDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_GETDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr25764Subsystem Vendor ID.Subsystem Vendor IDs can be obtained from the PCI SIG and are used to identify the vendor of the add-in card or subsystem. Values for the Subsystem ID are vendor-specific.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0000RSUBSYS_DEV_IDDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_MSBDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_LSBDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_RANGEDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_RESETDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_GETDBI_SLAVE_PF0_TYPE0_HDR_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr25779Subsystem ID.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31160x0000RregisterDBI_Slave.PF0_TYPE0_HDR.EXP_ROM_BASE_ADDR_REGEXP_ROM_BASE_ADDR_REGDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr258370x30R/W0x00000000DBI_Slave_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REGExpansion ROM BAR Register. This register handles the base address and size information for this expansion ROM.falsefalsefalsefalseROM_BAR_ENABLEDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_MSBDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_LSBDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_RESETDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_GETDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr25810Expansion ROM Enable.This bit controls whether or not the Function accepts accesses to its expansion ROM. - When this bit is 0b, the Function's expansion ROM address space is disabled. - When the bit is 1b, address decoding is enabled using the parameters in the other part of the Expansion ROM Base Address register.The Memory Space Enable bit in the Command register has precedence over the Expansion ROM Enable bit. A Function must claim accesses to its expansion ROM only if both the Memory Space Enable bit and the Expansion ROM Enable bit are set.Note: The access attributes of this field are as follows: - Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R 000x0R/WRSVDP_1DBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_MSBDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_LSBDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_RANGEDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_RESETDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_GETDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr25818Reserved for future use.1010x000REXP_ROM_BASE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_MSBDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_LSBDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_RANGEDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_RESETDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_GETDBI_SLAVE_PF0_TYPE0_HDR_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_SETDWC_pcie_wire_cpcie_usp_4x8.csr25836Expansion ROM Base Address.Upper 21 bits of the Expansion ROM base address.The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires.Note: The access attributes of this field are as follows: - Wire: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R - Dbi: if (EXP_ROM_BAR_MASK_REG.ROM_BAR_ENABLED == 1) then R/W else R 31110x000000R/WregisterDBI_Slave.PF0_TYPE0_HDR.PCI_CAP_PTR_REGPCI_CAP_PTR_REGDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr258710x34R0x00000040DBI_Slave_PF0_TYPE0_HDR_PCI_CAP_PTR_REGCapabilities Pointer Register. This register is used to point to a linked list of capabilities implemented by a Function.falsefalsefalsefalseCAP_POINTERDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_MSBDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_LSBDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_RANGEDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_RESETDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_GETDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_CAP_POINTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr25863Capabilities Pointer. This register points to a valid capability structure. Either this structure is the PCI Express Capability structure, or a subsequent list item points to the PCI Express Capability structure. The bottom two bits are reserved, the controller sets it to 00b. Software must mask these bits off before using this register as a pointer in Configuration Space to the first entry of a linked list of new capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.700x40RRSVDP_8DBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_MSBDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_LSBDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_RANGEDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_RESETDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_GETDBI_SLAVE_PF0_TYPE0_HDR_PCI_CAP_PTR_REG_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr25870Reserved for future use.3180x000000RregisterDBI_Slave.PF0_TYPE0_HDR.MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGMAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_OFFSETDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr259370x3CR/W0x000001ffDBI_Slave_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REGMax_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register. The Interrupt Line register communicates interrupt line routing information. The Interrupt Pin register identifies the legacy interrupt Message(s) the Function uses.falsefalsefalsefalseINT_LINEDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_MSBDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_LSBDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_RANGEDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_RESETDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_GETDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_SETDWC_pcie_wire_cpcie_usp_4x8.csr25891Interrupt Line.The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin.Values in this register are programmed by system software and are system architecture specific. The Function itself does not use this value; rather the value in this register is used by device drivers and operating systems.700xffR/WINT_PINDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_MSBDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_LSBDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_RANGEDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_RESETDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_GETDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_SETDWC_pcie_wire_cpcie_usp_4x8.csr25928Interrupt Pin.The Interrupt Pin register identifies the legacy interrupt Message(s) the Function uses.The valid values are: - 01h, 02h, 03h, and 04h: Map to legacy interrupt Messages for INTA, INTB, INTC, and INTD respectively. - 00h: Indicates that the Function uses no legacy interrupt Message(s). - 05h through FFh: Reserved.PCI Express defines one legacy interrupt Message for a single Function device and up to four legacy interrupt Messages for a multi-Function device. For a single Function device, only INTA may be used.Any Function on a multi-Function device can use any of the INTx Messages. If a device implements a single legacy interrupt Message, it must be INTA; if it implements two legacy interrupt Messages, they must be INTA and INTB; and so forth.For a multi-Function device, all Functions may use the same INTx Message or each may have its own (up to a maximum of four Functions) or any combination thereof. A single Function can never generate an interrupt request on more than one INTx Message.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x01RRSVDP_16DBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_WIDTHDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_MSBDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_LSBDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_RANGEDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_RESETDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_FIELD_MASKDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_GETDBI_SLAVE_PF0_TYPE0_HDR_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr25936Reserved for future use.31160x0000RgroupDBI_Slave.PF0_PM_CAPPF0_PM_CAPDBI_SLAVE_PF0_PM_CAP_ADDRESSDBI_SLAVE_PF0_PM_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_PM_CAP_OFFSETDBI_SLAVE_PF0_PM_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr263240x40R/WDBI_Slave_PF0_PM_CAPPF PCI Power Management Capability StructureregisterDBI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGregisterDBI_Slave.PF0_PM_CAP.CON_STATUS_REGregisterDBI_Slave.PF0_PM_CAP.CAP_ID_NXT_PTR_REGCAP_ID_NXT_PTR_REGDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_ADDRESSDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_OFFSETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr261300x0R0x03c35001DBI_Slave_PF0_PM_CAP_CAP_ID_NXT_PTR_REGPower Management Capabilities Register.falsefalsefalsefalsePM_CAP_IDDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_WIDTHDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_LSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_RANGEDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_RESETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_GETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr25957Capability ID.This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h.700x01RPM_NEXT_POINTERDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_WIDTHDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_LSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_RANGEDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_RESETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_GETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr25974Next Capability Pointer.This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list, this field is set to 00h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x50RPM_SPEC_VERDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_WIDTHDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_LSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_RANGEDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_RESETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_GETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SETDWC_pcie_wire_cpcie_usp_4x8.csr25991Version.This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0>.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.18160x3RPME_CLKDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_WIDTHDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_MSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_LSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_RANGEDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_RESETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_GETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_CLK_SETDWC_pcie_wire_cpcie_usp_4x8.csr26002PME Clock.Does not apply to PCI Express, the controller hardwires it to 0b.Note: This register field is sticky.19190x0R--20200x0rDSIDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_WIDTHDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_MSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_LSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_RANGEDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_RESETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_GETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_DSI_SETDWC_pcie_wire_cpcie_usp_4x8.csr26021Device Specific Initialization.The DSI bit indicates whether special initialization of this function is required.When set, indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized state.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.21210x0RAUX_CURRDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_WIDTHDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_MSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_LSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_RANGEDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_RESETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_GETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_AUX_CURR_SETDWC_pcie_wire_cpcie_usp_4x8.csr26054Aux_Current.This 3 bit field reports the Vaux auxiliary current requirements for the function.If this function implements the Data Register, the controller hardwires this field to 000b.If PME_Support is 0 xxxxb (PME assertion from D3cold is not supported), the controller hardwires this field to 0000b.For functions where PME_Support is 1 xxxxb (PME assertion from D3cold is supported), and which do not implement the Data field, the following encodings apply: - b111 375mA Vaux Max. Current Required - b110 320mA Vaux Max. Current Required - b101 270mA Vaux Max. Current Required - b100 220mA Vaux Max. Current Required - b011 160mA Vaux Max. Current Required - b010 100mA Vaux Max. Current Required - b001 55mA Vaux Max. Current Required - b000 0 self poweredNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.24220x7RD1_SUPPORTDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_WIDTHDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_LSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_RANGEDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_RESETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_GETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr26070D1_Support.If this bit is set, this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.25250x1RD2_SUPPORTDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_WIDTHDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_LSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_RANGEDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_RESETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_GETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr26086D2_Support.If this bit is set, this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26260x0RPME_SUPPORTDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_WIDTHDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_LSBDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_RANGEDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_RESETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_GETDBI_SLAVE_PF0_PM_CAP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr26129PME_Support.This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages.A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. - bit(27) X XXX1b - PME can be generated from D0 - bit(28) X XX1Xb - PME can be generated from D1 - bit(29) X X1XXb - PME can be generated from D2 - bit(30) X 1XXXb - PME can be generated from D3hot - bit(31) 1 XXXXb - PME can be generated from D3coldBit 31 (PME can be asserted from D3cold) represents a special case. Functions that set this bit require some sort of auxiliary power source. Implementation specific mechanisms are recommended to validate that the power source is available before setting this bit.Each bit that corresponds to a supported D-state must be set for PCI-PCI Bridge structures representing Ports on Root Complexes/Switches to indicate that the Bridge will forward PME Messages. Bit 31 must only be set if the Port is still able to forward PME Messages when main power is not available.The read value from this field is the write value && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where D1_SUPPORT and D2_SUPPORT are fields in this register.The reset value PME_SUPPORT_n && (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where PME_SUPPORT_n is a configuration parameter.Note: The access attributes of this field are as follows: - Wire: R - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3127RregisterDBI_Slave.PF0_PM_CAP.CON_STATUS_REGCON_STATUS_REGDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_ADDRESSDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_OFFSETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr263230x4R/W0x00000008DBI_Slave_PF0_PM_CAP_CON_STATUS_REGPower Management Control and Status Register.This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs.falsefalsefalsefalsePOWER_STATEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_WIDTHDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_MSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_LSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_RANGEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_RESETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_GETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_POWER_STATE_SETDWC_pcie_wire_cpcie_usp_4x8.csr26174PowerState.This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below.You can write to this register; however, the read-back value is the actual power state, not the write value. If you attempt to write an unsupported, optional state to this field, the write operation completes normally; however, the data is discarded and no state change occurs.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 10R/WfalsetruefalseD00x0D0 power stateD10x1D1 power stateD20x2D2 power stateD3hot0x3D3hot D3hot power stateRSVDP_2DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_WIDTHDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_MSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_LSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_RANGEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_RESETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_GETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr26182Reserved for future use.220x0RNO_SOFT_RSTDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_WIDTHDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_MSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_LSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_RANGEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_RESETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_GETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_NO_SOFT_RST_SETDWC_pcie_wire_cpcie_usp_4x8.csr26208No_Soft_Reset.This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set, this transition preserves internal function state. The function is in D0Active and no additional software intervention is required. - When clear, this transition results in undefined internal function state.Regardless of this bit, functions that transition from D3hot to D0 by Fundamental Reset will return to D0Uninitialized with only PME context preserved if PME is supported and enabled.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.330x1RRSVDP_4DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_WIDTHDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_MSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_LSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_RANGEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_RESETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_GETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr26216Reserved for future use.740x0RPME_ENABLEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_WIDTHDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_MSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_LSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_RANGEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_RESETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_GETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr26237PME_En. - When set, the function is permitted to generate a PME. - When clear, the function is not permitted to generate a PME.If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is available this bit is RWS and the bit is not modified by Conventional Reset or FLR.If PME_Support is 0 xxxxb, this field is not sticky (RW).If PME_Support is 0 0000b, the controller hardwires this bit to 0b.Note: This register field is sticky.88R/WDATA_SELECTDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_WIDTHDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_MSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_LSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_RANGEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_RESETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_GETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr26249Data_Select.This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented, this field must be hardwired to 0000b.1290x0RDATA_SCALEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_WIDTHDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_MSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_LSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_RANGEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_RESETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_GETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr26263Data_Scale.This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details, see 7.5.2.3 section of PCI Express Base Specification.14130x0RPME_STATUSDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_WIDTHDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_MSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_LSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_RANGEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_RESETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_GETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_PME_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr26282PME_Status.This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit.If PME_Support bit 31 of the Power Management Capabilities register is clear, this bit is permitted to be hardwired to 0b.Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this register value is not modified by Conventional Reset or FLR.15150x0R/W1CRSVDP_16DBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_WIDTHDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_MSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_LSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_RANGEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_RESETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_GETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr26290Reserved for future use.21160x00RB2_B3_SUPPORTDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_WIDTHDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_MSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_LSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_RANGEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_RESETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_GETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_B2_B3_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr26300B2B3 Support for D3hot.For a description of this standard PCIe register field, see the PCI Express Base Specification.22220x0RBUS_PWR_CLK_CON_ENDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_WIDTHDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_LSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_RANGEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_RESETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_GETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr26310Bus Power/Clock Control Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.23230x0RDATA_REG_ADD_INFODBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_WIDTHDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_MSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_LSBDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_RANGEDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_RESETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_FIELD_MASKDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_GETDBI_SLAVE_PF0_PM_CAP_CON_STATUS_REG_DATA_REG_ADD_INFO_SETDWC_pcie_wire_cpcie_usp_4x8.csr26322Data.This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field.31240x00RgroupDBI_Slave.PF0_MSI_CAPPF0_MSI_CAPDBI_SLAVE_PF0_MSI_CAP_ADDRESSDBI_SLAVE_PF0_MSI_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_MSI_CAP_OFFSETDBI_SLAVE_PF0_MSI_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr267220x50R/WDBI_Slave_PF0_MSI_CAPPF MSI Capability StructureregisterDBI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGregisterDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGregisterDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGregisterDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGregisterDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGregisterDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGregisterDBI_Slave.PF0_MSI_CAP.PCI_MSI_CAP_ID_NEXT_CTRL_REGPCI_MSI_CAP_ID_NEXT_CTRL_REGDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_ADDRESSDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_OFFSETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr265030x0R/W0x038a7005DBI_Slave_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REGMSI Capability Header and Message Control Register.falsefalsefalsefalsePCI_MSI_CAP_IDDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_WIDTHDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_LSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_RANGEDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_RESETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_GETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr26342Capability ID.Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure.700x05RPCI_MSI_CAP_NEXT_OFFSETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_LSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_RESETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_GETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr26359Next Capability Pointer.This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x70RPCI_MSI_ENABLEDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_WIDTHDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_LSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_RANGEDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_RESETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_GETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr26376MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear, the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit to enable MSI. A device driver is prohibited from writing this bit to mask a function's service request. For more details on control of INTx interrupts, see section 7.5.1.1 of PCI Express Base Specification. - If clear, the function is prohibited from using MSI to request service.16160x0R/WPCI_MSI_MULTIPLE_MSG_CAPDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_WIDTHDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_LSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_RANGEDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_RESETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_GETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr26402Multiple Message Capable.System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors, it requests four by initializing this field to 010b). The encoding is defined as: - 000b: 1 vector requested - 001b: 2 vectors requested - 010b: 4 vectors requested - 011b: 8 vectors requested - 100b: 16 vectors requested - 101b: 32 vectors requested - 110b: Reserved - 111b: ReservedNote: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.19170x5RPCI_MSI_MULTIPLE_MSG_ENDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_WIDTHDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_LSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_RANGEDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_RESETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_GETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr26427Multiple Message Enable.Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a function requests four vectors (indicated by a Multiple Message Capable encoding of 010b), system software can allocate either four, two, or one vector by writing a 010b, 001b, or 000b to this field, respectively. When MSI is enabled, a function will be allocated at least 1 vector. The encoding is defined as: - 000b: 1 vector allocated - 001b: 2 vectors allocated - 010b: 4 vectors allocated - 011b: 8 vectors allocated - 100b: 16 vectors allocated - 101b: 32 vectors allocated - 110b: Reserved - 111b: Reserved22200x0R/WPCI_MSI_64_BIT_ADDR_CAPDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_WIDTHDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_LSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_RANGEDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_RESETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_GETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr2644764 bit address capable. - If set, the function is capable of sending a 64-bit message address. - If clear, the function is not capable of sending a 64-bit message address.This bit must be set if the function is a PCI Express Endpoint.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.23230x1RPCI_PVM_SUPPORTDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_WIDTHDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_LSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_RANGEDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_RESETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_GETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr26460Per-Vector Masking Capable. - If set, the function supports MSI Per-Vector Masking. - If clear, the function does not support MSI Per-Vector Masking.This bit must be set if the function is a PF or VF within an SR-IOV Device.24240x1RPCI_MSI_EXT_DATA_CAPDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_WIDTHDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_LSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_RANGEDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_RESETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_GETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr26477Extended Message Data Capable. - If set, the function is capable of providing Extended Message Data. - If clear, the function does not support providing Extended Message Data.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.25250x1RPCI_MSI_EXT_DATA_ENDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_WIDTHDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_LSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_RANGEDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_RESETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_GETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr26494Extended Message Data Enable. - If set, the function is enabled to provide Extended Message Data. - If clear, the function is not enabled to provide Extended Message Data.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO - Dbi: PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO 26260x0R/WRSVDP_27DBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETDBI_SLAVE_PF0_MSI_CAP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr26502Reserved for future use.31270x00RregisterDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_04H_REGMSI_CAP_OFF_04H_REGDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_ADDRESSDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_OFFSETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr265310x4R/W0x00000000DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_04H_REGMessage Address Register for MSI (Offset 04h).falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_WIDTHDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_MSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_LSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_RANGEDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_RESETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_GETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr26514Reserved for future use.100x0RPCI_MSI_CAP_OFF_04HDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_WIDTHDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_LSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_RANGEDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_RESETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_GETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SETDWC_pcie_wire_cpcie_usp_4x8.csr26530Message Address - System-specified message address.If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set, the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI transaction. Address[1:0] are set to 00b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 3120x00000000R/WregisterDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_08H_REGMSI_CAP_OFF_08H_REGDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_ADDRESSDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_OFFSETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr266110x8R/W0x00000000DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_08H_REGFor a function that supports a 32-bit message address, - bits[31:16] of this register represent the Extended Message Data, and - bits[15:0] of this register represent the Message DataFor a function that supports a 64-bit message address (bit 23 in PCI_MSI_CAP_ID_NEXT_CTRL_REG register set), this register represents the Message Upper Address Register for MSI (Offset 08h). It specifies the Message Upper Address (System-specified message upper address). This register is required for PCI Express Endpoints and is optional for other function types. If the Message Enable bit (bit 0 of the Message Control register) is set, the contents of this register (if non-zero) specify the upper 32-bits of a 64-bit message address (Address[63:32]). If the contents of this register are zero, the Function uses the 32 bit address specified by the Message Address register.falsefalsefalsefalsePCI_MSI_CAP_OFF_08HDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_WIDTHDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_LSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_RANGEDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_RESETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_GETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SETDWC_pcie_wire_cpcie_usp_4x8.csr26581For a function that supports a 32-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.For a function that supports a 64-bit message address, it contains lower 16 bits of the Message Upper Address.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R 1500x0000R/WPCI_MSI_CAP_OFF_0AHDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_WIDTHDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_LSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_RANGEDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_RESETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_GETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SETDWC_pcie_wire_cpcie_usp_4x8.csr26610For a function that supports a 32-bit message address, this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is outside the MSI Capability structure and undefined. For the MSI Capability structures with Per-vector Masking, it must be implemented if the Extended Message Data Capable bit is set; otherwise, it is RsvdP. If the Extended Message Data Enable bit (bit 26 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the DWORD Memory Write transaction uses Extended Message Data for the upper 16 bits; otherwise, it uses 0000h for the upper 16 bits.For a function that supports a 64-bit message address, it contains upper 16 bits of the Message Upper Address.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R 31160x0000R/WregisterDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_0CH_REGMSI_CAP_OFF_0CH_REGDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_ADDRESSDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_OFFSETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr266760xCR/W0x00000000DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REGFor a function that supports a 32-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message address, this register contains Message Data.falsefalsefalsefalsePCI_MSI_CAP_OFF_0CHDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_WIDTHDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_LSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_RANGEDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_RESETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_GETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SETDWC_pcie_wire_cpcie_usp_4x8.csr26654For a function that supports a 32-bit message address, this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set, the function sends a DWORD Memory Write transaction using Message Data for the lower 16 bits. All 4 Byte Enables are set. The Multiple Message Enable field (bits 22:20 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) defines the number of low order message data bits the function is permitted to modify to generate its system software allocated vectors. For example, a Multiple Message Enable encoding of 010b indicates the function has been allocated four vectors and is permitted to modify message data bits 1 and 0 (a function modifies the lower message data bits to generate the allocated number of vectors). If the Multiple Message Enable field is 000b, the Function is not permitted to modify the message data.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R 1500x0000R/WPCI_MSI_CAP_OFF_0EHDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_WIDTHDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_LSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_RANGEDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_RESETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_GETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SETDWC_pcie_wire_cpcie_usp_4x8.csr26675For a function that supports a 32-bit message address, this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set.For a function that supports a 64-bit message address, this field contains Message Data (System-specified message data).Note: The access attributes of this field are as follows: - Wire: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO - Dbi: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW : RO 31160x0000R/WregisterDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_10H_REGMSI_CAP_OFF_10H_REGDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_ADDRESSDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_OFFSETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr267050x10R/W0x00000000DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_10H_REGFor a function that supports a 32-bit message address, this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.falsefalsefalsefalsePCI_MSI_CAP_OFF_10HDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_WIDTHDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_LSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_RANGEDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_RESETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_GETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SETDWC_pcie_wire_cpcie_usp_4x8.csr26704Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit, contains Mask Bits.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R - Dbi: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R 3100x00000000R/WregisterDBI_Slave.PF0_MSI_CAP.MSI_CAP_OFF_14H_REGMSI_CAP_OFF_14H_REGDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_ADDRESSDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_OFFSETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr267210x14R0x00000000DBI_Slave_PF0_MSI_CAP_MSI_CAP_OFF_14H_REGPending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.falsefalsefalsefalsePCI_MSI_CAP_OFF_14HDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_WIDTHDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_LSBDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_RANGEDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_RESETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_FIELD_MASKDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_GETDBI_SLAVE_PF0_MSI_CAP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SETDWC_pcie_wire_cpcie_usp_4x8.csr26720Pending Bits. For each pending bit that is set, the function has a pending associated message.3100x00000000RgroupDBI_Slave.PF0_PCIE_CAPPF0_PCIE_CAPDBI_SLAVE_PF0_PCIE_CAP_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_OFFSETDBI_SLAVE_PF0_PCIE_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr294970x70R/WDBI_Slave_PF0_PCIE_CAPPF PCI Express Capability StructureregisterDBI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGregisterDBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGregisterDBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSregisterDBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGregisterDBI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGregisterDBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGregisterDBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGregisterDBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGregisterDBI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGregisterDBI_Slave.PF0_PCIE_CAP.PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_OFFSETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr268790x0R0x0002b010DBI_Slave_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REGPCI Express Capabilities, ID, Next Pointer Register.falsefalsefalsefalsePCIE_CAP_IDDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_WIDTHDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_LSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_RANGEDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_RESETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_GETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr26740Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure.700x10RPCIE_CAP_NEXT_PTRDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_WIDTHDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_LSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_RANGEDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_RESETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_GETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SETDWC_pcie_wire_cpcie_usp_4x8.csr26755Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580xb0RPCIE_CAP_REGDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_WIDTHDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_LSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_RANGEDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_RESETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_GETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SETDWC_pcie_wire_cpcie_usp_4x8.csr26779Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number.A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example, through a new Capability field) is permitted to increment this field. All such changes to the PCI Express Capability structure must be software-compatible. Software must check for Capability Version numbers that are greater than or equal to the highest number defined when the software is written, as functions reporting any such Capability Version numbers will contain a PCI Express Capability structure that is compatible with that piece of software.The controller hardwires this field to 2h for functions compliant to PCI Express Base Specification, Revision 4.0, Version 1.0.Note: This register field is sticky.19160x2RPCIE_DEV_PORT_TYPEDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_LSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_RANGEDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_RESETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_GETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr26806Device/Port Type. Indicates the specific type of this PCI Express function.Note: Different functions in a Multi-Function Device can generally be of different types.Defined encodings for functions that implement a Type 00h PCI Configuration Space header are: - 0000b PCI Express Endpoint - 0001b Legacy PCI Express EndpointDefined encodings for functions that implement a Type 01h PCI Configuration Space header are: - 0100b Root Port of PCI Express Root Complex - 0101b Upstream Port of PCI Express Switch - 0110b Downstream Port of PCI Express SwitchAll other encodings are Reserved.Note: Different Endpoint types have notably different requirements in Section 1.3.2 of PCI Express Base Specification regarding I/O resources, Extended Configuration Space, and other capabilities.2320RPCIE_SLOT_IMPDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_WIDTHDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_LSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_RANGEDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_RESETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_GETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SETDWC_pcie_wire_cpcie_usp_4x8.csr26822Slot Implemented. When set, this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit is undefined for Upstream Ports.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 24240x0RPCIE_INT_MSG_NUMDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_WIDTHDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_LSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_RANGEDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_RESETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_GETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SETDWC_pcie_wire_cpcie_usp_4x8.csr26864PCIE Interrupt Message Number.For a description of this standard PCIe register field, see the PCI Express Base Specification.Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message generated in association with any of the status bits of this Capability structure.For MSI, the value in this field indicates the offset between the base Message Data and the interrupt message that is generated. Hardware is required to update this field so that it is correct if the number of MSI Messages assigned to the Function changes when software writes to the Multiple Message Enable field in the MSI Message Control register.For MSI-X, the value in this field indicates which MSI-X Table entry is used to generate the interrupt message. The entry must be one of the first 32 entries even if the Function implements more than 32 entries. For a given MSI-X implementation, the entry must remain constant.If both MSI and MSI-X are implemented, they are permitted to use different vectors, though software is permitted to enable only one mechanism at a time. If MSI-X is enabled, the value in this field must indicate the vector for MSI-X. If MSI is enabled or neither is enabled, the value in this field must indicate the vector for MSI. If software enables both MSI and MSI-X at the same time, the value in this field is undefined.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.29250x00RRSVDDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_WIDTHDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_LSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_RANGEDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_RESETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_GETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SETDWC_pcie_wire_cpcie_usp_4x8.csr26871Reserved.30300x0RRSVDP_31DBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_WIDTHDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_MSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_LSBDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_RANGEDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_RESETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_GETDBI_SLAVE_PF0_PCIE_CAP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr26878Reserved for future use.31310x0RregisterDBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES_REGDEVICE_CAPABILITIES_REGDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_OFFSETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr271690x4R0x00008fe1DBI_Slave_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REGDevice Capabilities Register.The Device Capabilities register identifies PCI Express device function specific capabilities.falsefalsefalsefalsePCIE_CAP_MAX_PAYLOAD_SIZEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr26911Max_Payload_Size Supported.This field indicates the maximum payload size that the function can support for TLPs.Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max payload size - 011b: 1024 bytes max payload size - 100b: 2048 bytes max payload size - 101b: 4096 bytes max payload size - 110b: Reserved - 111b: ReservedThe functions of a Multi-Function Device are permitted to report different values for this field.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x1RPCIE_CAP_PHANTOM_FUNC_SUPPORTDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr26965Phantom Functions Supported.This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom Functions) with the Tag identifier (see Section 2.2.6.2 of PCI Express Base Specification for a description of Tag Extensions).With every Function in an ARI Device, the Phantom Functions Supported field must be set to 00b. The remainder of this field description applies only to non-ARI Multi-Function Devices.This field indicates the number of most significant bits of the Function Number portion of Requester ID that are logically combined with the Tag identifier.Defined encodings are: - 00b: No Function Number bits are used for Phantom Functions. Multi-Function Devices are permitted to implement up to 8 independent functions. - 01b: The most significant bit of the Function number in Requester ID is used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-3. Functions 0, 1, 2, and 3 are permitted to use Function Numbers 4, 5, 6, and 7 respectively as Phantom Functions. - 10b: The two most significant bits of Function Number in Requester ID are used for Phantom Functions; a Multi-Function Device is permitted to implement Functions 0-1. Function 0 is permitted to use Function Numbers 2, 4, and 6 for Phantom Functions. Function 1 is permitted to use Function Numbers 3, 5, and 7 as Phantom Functions. - 11b: All 3 bits of Function Number in Requester ID used for Phantom Functions. The device must have a single Function 0 that is permitted to use all other Function Numbers as Phantom Functions.Note: Phantom Function support for the function must be enabled by the Phantom Functions Enable field in the Device Control register before the Function is permitted to use the Function Number field in the Requester ID for Phantom Functions.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.430x0RPCIE_CAP_EXT_TAG_SUPPDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SETDWC_pcie_wire_cpcie_usp_4x8.csr26992Extended Tag Field Supported.This bit, in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register, indicates the maximum supported size of the Tag field as a Requester. This bit must be set if the 10-Bit Tag Requester Supported bit is set.Defined encodings are: - 0b: 5-bit Tag field supported - 1b: 8-bit Tag field supportedNote: 8-bit Tag field generation must be enabled by the Extended Tag Field Enable bit in the Device Control register of the Requester Function before 8-bit Tags can be generated by the Requester. See Section 2.2.6.2 of PCI Express Base Specificationfor interactions with enabling the use of 10-Bit Tags.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.550x1RPCIE_CAP_EP_L0S_ACCPT_LATENCYDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_SETDWC_pcie_wire_cpcie_usp_4x8.csr27027Endpoint L0s Acceptable Latency. This field indicates the acceptable total latency that an Endpoint can withstand due to the transition from L0s state to the L0 state. It is essentially an indirect measure of the Endpoint’s internal buffering.Power management software uses the reported L0s Acceptable Latency number to compare against the L0s exit latencies reported by all components comprising the data path from this Endpoint to the Root Complex Root Port to determine whether ASPM L0s entry can be used with no loss of performance.Defined encodings are: - 000b: Maximum of 64 ns - 001b: Maximum of 128 ns - 010b: Maximum of 256 ns - 011b: Maximum of 512 ns - 100b: Maximum of 1 us - 101b: Maximum of 2 us - 110b: Maximum of 4 us - 111b: No limitFor functions other than Endpoints, this field is Reserved and the controller hardwires it to 000b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.860x7RPCIE_CAP_EP_L1_ACCPT_LATENCYDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_SETDWC_pcie_wire_cpcie_usp_4x8.csr27062Endpoint L1 Acceptable Latency. This field indicates the acceptable latency that an Endpoint can withstand due to the transition from L1 state to the L0 state. It is essentially an indirect measure of the Endpoint’s internal buffering.Power management software uses the reported L1 Acceptable Latency number to compare against the L1 Exit Latencies reported (see below) by all components comprising the data path from this Endpoint to the Root Complex Root Port to determine whether ASPM L1 entry can be used with no loss of performance.Defined encodings are: - 000b: Maximum of 1 us - 001b Maximum of 2 us - 010b Maximum of 4 us - 011b Maximum of 8 us - 100b Maximum of 16 us - 101b Maximum of 32 us - 110b Maximum of 64 us - 111b No limitFor functions other than Endpoints, this field is Reserved and the controller hardwires it to 000b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W (Sticky) else R(Sticky) Note: This register field is sticky.1190x7RRSVDP_12DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr27069Reserved for future use.14120x0RPCIE_CAP_ROLE_BASED_ERR_REPORTDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr27089Role-Based Error Reporting. When set, this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification, Revision 1.0a, and later incorporated into PCI Express Base Specification, Revision 1.1. This bit must be set by all functions conforming to the ECN, PCI Express Base Specification, Revision 1.1., or subsequent PCI Express Base Specification revisions.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.15150x1RRSVDP_16DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr27096Reserved for future use.17160x0RPCIE_CAP_CAP_SLOT_PWR_LMT_VALUEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr27122Captured Slot Power Limit Value.For a description of this standard PCIe register field, see the PCI Express Base Specification.Captured Slot Power Limit Value (Upstream Ports only). In combination with the Captured Slot Power Limit Scale value, specifies the upper limit on power available to the adapter.Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Captured Slot Power Limit Scale field except when the Captured Slot Power Limit Scale field equals 00b (1.0x) and the Captured Slot Power Limit Value exceeds EFh, then alternative encodings are used (for more details, see section 7.5.3.9 of PCI Express Base Specification).This value is set by the Set_Slot_Power_Limit Message or hardwired to 00h (for more details, see section 6.9 of PCI Express Base Specification).2518RPCIE_CAP_CAP_SLOT_PWR_LMT_SCALEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr27142Captured Slot Power Limit Scale.For a description of this standard PCIe register field, see the PCI Express Base Specification.Captured Slot Power Limit Scale (Upstream Ports only). Specifies the scale used for the Slot Power Limit Value.Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001xThis value is set by the Set_Slot_Power_Limit Message or hardwired to 00b (for more details, see section 6.9 of PCI Express Base Specification).2726RPCIE_CAP_FLR_CAPDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr27161Function Level Reset Capability. A value of 1b indicates the function supports the optional Function Level Reset mechanism described in section 6.6.2 of of PCI Express Base Specification.This bit applies to Endpoints only. For all other function types the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.28280x0RRSVDP_29DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES_REG_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr27168Reserved for future use.31290x0RregisterDBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL_DEVICE_STATUSDEVICE_CONTROL_DEVICE_STATUSDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_BYTE_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_OFFSETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr275180x8R/W0x00002010DBI_Slave_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUSDevice Control and Device Status Register.This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters.falsefalsefalsefalsePCIE_CAP_CORR_ERR_REPORT_ENDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr27192Correctable Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_COR Messages (for more details, see section 6.2.5, section 6.2.6, and section 6.2.10.2 of PCI Express Base Specification). For a Multi-Function device, this bit controls error reporting for each function from point-of-view of the respective function.For a Root Port, the reporting of correctable errors is internal to the root. No external ERR_COR Message is generated.000x0R/WPCIE_CAP_NON_FATAL_ERR_REPORT_ENDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr27209Non-Fatal Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_NONFATAL Messages (for more details, see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a Multi-Function Device, this bit controls error reporting for each function from point-of-view of the respective Function.For a Root Port, the reporting of Non-fatal errors is internal to the root. No external ERR_NONFATAL Message is generated.110x0R/WPCIE_CAP_FATAL_ERR_REPORT_ENDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr27225Fatal Error Reporting Enable.This bit, in conjunction with other bits, controls sending ERR_FATAL Messages (for more details, see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function device, this bit controls error reporting for each function from point-of-view of the respective function.For a Root Port, the reporting of Fatal errors is internal to the root. No external ERR_FATAL Message is generated.220x0R/WPCIE_CAP_UNSUPPORT_REQ_REP_ENDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr27239Unsupported Request Reporting Enable.This bit, in conjunction with other bits, controls the signaling of Unsupported Request Errors by sending error Messages (for more details, see section 6.2.5 and section 6.2.6 of PCI Express Base Specification). For a Multi-Function Device, this bit controls error reporting for each Function from point-of-view of the respective Function.330x0R/WPCIE_CAP_EN_REL_ORDERDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SETDWC_pcie_wire_cpcie_usp_4x8.csr27259Enable Relaxed Ordering.If this bit is set, the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details, see section 2.2.6.4 and section 2.4 of PCI Express Base Specification).For a function that never sets the Relaxed Ordering attribute in transactions it initiates as a Requester, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 440x1R/WPCIE_CAP_MAX_PAYLOAD_SIZE_CSDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SETDWC_pcie_wire_cpcie_usp_4x8.csr27296Max_Payload_Size.This field sets maximum TLP payload size for the Function. As a Receiver, the Function must handle TLPs as large as the set value. As a Transmitter, the Function must not generate TLPs exceeding the set value. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities (DEVICE_CAPABILITIES_REG) register (for more details, see section 7.5.3.3 of PCI Express Base Specification).Defined encodings for this field are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max payload size - 011b: 1024 bytes max payload size - 100b: 2048 bytes max payload size - 101b: 4096 bytes max payload size - 110b: Reserved - 111b: ReservedFor Functions that support only the 128-byte max payload size, the controller hardwires this field to 000b.System software is not required to program the same value for this field for all the Functions of a Multi-Function device (for more details, see section 2.2.2 of PCI Express Base Specification).For ARI Devices, Max_Payload_Size is determined solely by the setting in Function0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.750x0R/WPCIE_CAP_EXT_TAG_ENDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr27329Extended Tag Field Enable.This bit, in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register, determines how many Tag field bits a Requester is permitted to use.When the 10-Bit Tag Requester Enable bit is clear, - If the Extended Tag Field Enable bit is set, the function is permitted to use an 8-bit Tag field as a Requester - If the Extended Tag Field Enable bit is clear, the Function is restricted to a 5-bit Tag fieldSee section 2.2.6.2 of PCI Express Base Specification for required behavior when the 10-Bit Tag Requester Enable bit is set.If software changes the value of the Extended Tag Field Enable bit while the function has outstanding Non-Posted Requests, the result is undefined.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO 88R/WPCIE_CAP_PHANTOM_FUNC_ENDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr27365Phantom Functions Enable.This bit, in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register, determines how many Tag field bits a Requester is permitted to use.When the 10-Bit Tag Requester Enable bit is clear, - If this bit is set, it enables a function to use unclaimed functions as Phantom functions to extend the number of outstanding transaction identifiers - If this bit is clear, the function is not allowed to use Phantom functionsFor more details, see section 2.2.6.2 of PCI Express Base Specification.Software should not change the value of this bit while the function has outstanding Non-Posted Requests; otherwise, the result is undefined.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO 99RPCIE_CAP_AUX_POWER_PM_ENDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr27392Aux Power PM Enable.This bit is derived by sampling the sys_aux_pwr_det input.When set this bit, enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems should continue to indicate PME Aux power requirements. Aux power is allocated as requested in the Aux_Current field of the Power Management Capabilities register (PMC), independent of the PME_En bit in the Power Management Control/Status register (PMCSR). For Multi-Function devices, a component is allowed to draw Aux power if at least one of the functions has this bit set.Note: Functions that consume Aux power must preserve the value of this sticky register when Aux power is available. In such functions, this bit is not modified by Conventional Reset.For functions that do not implement this capability, the controller hardwires this bit to 0b.Note: This register field is sticky.1010R/WPCIE_CAP_EN_NO_SNOOPDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SETDWC_pcie_wire_cpcie_usp_4x8.csr27419Enable No Snoop.If this bit is set, the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express Base Specification).Note: Setting this bit to 1b should not cause a function to set the No Snoop attribute on all transactions that it initiates. Even when this bit is set, a function is only permitted to set the No Snoop attribute on a transaction when it can guarantee that the address of the transaction is not stored in any cache in the system.The controller hardwires this bit 0b if a function would never set the No Snoop attribute in transactions it initiates.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 11110x0RPCIE_CAP_MAX_READ_REQ_SIZEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr27442Max_Read_Request_Size.This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: - 000b: 128 bytes maximum Read Request size - 001b: 256 bytes maximum Read Request size - 010b: 512 bytes maximum Read Request size - 011b: 1024 bytes maximum Read Request size - 100b: 2048 bytes maximum Read Request size - 101b: 4096 bytes maximum Read Request size - 110b: Reserved - 111b: ReservedFor functions that do not generate Read Requests larger than 128 bytes and functions that do not generate Read Requests on their own behalf, the controller implements this field as Read Only (RO) with a value of 000b.14120x2R/W--16150x0rPCIE_CAP_NON_FATAL_ERR_DETECTEDDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr27460Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device, each function indicates status of errors as perceived by the respective Function.For functions supporting Advanced Error Handling, errors are logged in this register regardless of the settings of the Uncorrectable Error Mask register.17170x0R/W1C--18180x0rPCIE_CAP_UNSUPPORTED_REQ_DETECTEDDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr27475Unsupported Request Detected.This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function Device, each function indicates status of errors as perceived by the respective function.19190x0R/W1CPCIE_CAP_AUX_POWER_DETECTEDDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr27488AUX Power Detected.Functions that require Aux power report this bit as set if Aux power is detected by the function.This bit is derived by sampling the sys_aux_pwr_det input.2020RPCIE_CAP_TRANS_PENDINGDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SETDWC_pcie_wire_cpcie_usp_4x8.csr27509Transactions Pending.Endpoints:When set, this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have completed or have been terminated by the Completion Timeout mechanism. This bit must also be cleared upon the completion of an FLR.Root and Switch Ports:The controller hardwires this bit to 0b.2121RRSVDP_22DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr27517Reserved for future use.31220x000RregisterDBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES_REGLINK_CAPABILITIES_REGDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_OFFSETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr278690xCR0x00400c84DBI_Slave_PF0_PCIE_CAP_LINK_CAPABILITIES_REGLink Capabilities Register.The Link Capabilities register identifies PCI Express Link specific capabilities.falsefalsefalsefalsePCIE_CAP_MAX_LINK_SPEEDDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SETDWC_pcie_wire_cpcie_usp_4x8.csr27558Max Link Speed.This field indicates the maximum Link speed of the associated Port.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the maximum Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are reserved.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.300x4RPCIE_CAP_MAX_LINK_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr27594Maximum Link Width.This field indicates the maximum Link width (xN – corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port), adapter connector (Upstream Port), or in the case of component-to-component connections, the actual wired connection width.Defined encodings are: - 00 0001b x1 - 00 0010b x2 - 00 0100b x4 - 00 1000b x8 - 00 1100b x12 - 01 0000b x16 - 10 0000b x32All other encodings are Reserved.Multi-Function devices associated with an Upstream Port must report the same value in this field for all functions.For a description of this standard PCIe register field, see the PCI Express Base Specification.In M-PCIe mode, the reset and dynamic values of this field are calculated by the controller.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.940x08RPCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORTDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr27619Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements, see section 5.4.1 of PCI Express Base Specification.Defined encodings are: - 00b: No ASPM Support - 01b: L0s Supported - 10b: L1 Supported - 11b: L0s and L1 SupportedMulti-Function devices associated with an Upstream Port must report the same value in this field for all functions.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.11100x3RPCIE_CAP_L0S_EXIT_LATENCYDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SETDWC_pcie_wire_cpcie_usp_4x8.csr27677L0s Exit Latency.This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported, the value is undefined; however, see the Implementation Note "Potential Issues With Legacy Software When L0s is Not Supported" in section 5.4.1.1 of PCI Express Base Specification for the recommended value.Defined encodings are: - 000b: Less than 64 ns - 001b: 64 ns to less than 128 ns - 010b: 128 ns to less than 256 ns - 011b: 256 ns to less than 512 ns - 100b: 512 ns to less than 1 us - 101b: 1 us to less than 2 us - 110b: 2 us to 4 us - 111b: More than 4 usNote: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.There are two each of these register fields, this one and a shadow one at the same address.The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request.Common Clock operation is supported (possible) in the controller when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYCommon Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG).The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1412RPCIE_CAP_L1_EXIT_LATENCYDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SETDWC_pcie_wire_cpcie_usp_4x8.csr27731L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported, the value is undefined.Defined encodings are: - 000b: Less than 1us - 001b: 1 us to less than 2 us - 010b: 2 us to less than 4 us - 011b: 4 us to less than 8 us - 100b: 8 us to less than 16 us - 101b: 16 us to less than 32 us - 110b: 32 us to 64 us - 111b: More than 64 μsNote: Exit latencies may be influenced by PCI Express reference clock configuration depending upon whether a component uses a common or separate reference clock.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.There are two each of these register fields, this one and a shadow one at the same address.The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is accessed by a read request.Common Clock operation is supported (possible) in the controller when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYCommon Clock operation is enabled in the controller when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG).The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1715RPCIE_CAP_CLOCK_POWER_MANDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SETDWC_pcie_wire_cpcie_usp_4x8.csr27769Clock Power Management. For Upstream Ports, a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the "clock request" (CLKREQ#) mechanism when the Link is in the L1 and L2/L3 Ready Link states. A value of 0b indicates the component does not have this capability and that reference clock(s) must not be removed in these Link states.L1 PM Substates defines other semantics for the CLKREQ# signal, which are managed independently of Clock Power Management.This Capability is applicable only in form factors that support "clock request" (CLKREQ#) capability.For a Multi-Function device associated with an Upstream Port, each Function indicates its capability independently. Power Management configuration software must only permit reference clock removal if all functions of the Multi-Function device indicate a 1b in this bit. For ARI Devices, all Functions must indicate the same value in this bit.For Downstream Ports, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RPCIE_CAP_SURPRISE_DOWN_ERR_REP_CAPDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr27785Surprise Down Error Reporting Capable. For a Downstream Port, this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition.For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.Note: This register field is sticky.19190x0RPCIE_CAP_DLL_ACTIVE_REP_CAPDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr27804Data Link Layer Link Active Reporting Capable. For a Downstream Port, the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. For a hot-plug capable Downstream Port (as indicated by the Hot-Plug Capable bit of the Slot Capabilities register) or a Downstream Port that supports Link speeds greater than 5.0 GT/s, the controller hardwires this bit to 1b.For Upstream Ports and components that do not support this optional capability, the controller hardwires this bit to 0b.20200x0RPCIE_CAP_LINK_BW_NOT_CAPDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr27826Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting Links wider than x1 and/or multiple Link speeds.This field is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability the controller hardwires this bit to 0b.Note: This register field is sticky.21210x0RPCIE_CAP_ASPM_OPT_COMPLIANCEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr27845ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b.Software is permitted to use the value of this bit to help determine whether to enable ASPM or whether to run ASPM compliance tests.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 22220x1RRSVDP_23DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr27852Reserved for future use.23230x0RPCIE_CAP_PORT_NUMDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SETDWC_pcie_wire_cpcie_usp_4x8.csr27868Port Number. This field indicates the PCI Express Port number for the given PCI Express Link.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31240x00RregisterDBI_Slave.PF0_PCIE_CAP.LINK_CONTROL_LINK_STATUS_REGLINK_CONTROL_LINK_STATUS_REGDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_OFFSETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr284210x10R/W0x10000000DBI_Slave_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REGLink Control and Link Status Register.This register controls and provides information about PCI Express Link specific parameters.falsefalsefalsefalsePCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROLDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SETDWC_pcie_wire_cpcie_usp_4x8.csr27919Active State Power Management (ASPM) Control.This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to enable ASPM.Defined encodings are: - 00b: Disabled - 01b: L0s Entry Enabled - 10b: L1 Entry Enabled - 11b: L0s and L1 Entry EnabledNote: "L0s Entry Enabled" enables the Transmitter to enter L0s. If L0s is supported, the Receiver must be capable of entering L0s even when the Transmitter is disabled from entering L0s (00b or 10b).ASPM L1 must be enabled by software in the Upstream component on a Link prior to enabling ASPM L1 in the Downstream component on that Link. When disabling ASPM L1, software must disable ASPM L1 in the Downstream component on a Link prior to disabling ASPM L1 in the Upstream component on that Link. ASPM L1 must only be enabled on the Downstream component if both components on a Link support ASPM L1.For Multi-Function Devices (including ARI Devices), it is recommended that software program the same value for this field in all Functions. For non-ARI Multi-Function Devices, only capabilities enabled in all Functions are enabled for the component as a whole.For ARI Devices, ASPM Control is determined solely by the setting in Function0, regardless of Function 0's D-state. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.Software must not enable L0s in either direction on a given Link unless components on both sides of the Link each support L0s; otherwise, the result is undefined.100x0R/WRSVDP_2DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr27927Reserved for future use.220x0RPCIE_CAP_RCBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SETDWC_pcie_wire_cpcie_usp_4x8.csr27967Read Completion Boundary (RCB).Root Ports:Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB.Defined encodings are: - 0b: 64 byte - 1b: 128 byteThe controller hardwires this bit for a Root Port and returns its RCB support capabilities.Endpoints and Bridges:Optionally set by configuration software to indicate the RCB value of the Root Port Upstream from the Endpoint or Bridge. Refer to Section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB.Defined encodings are: - 0b 64 byte - 1b 128 byteConfiguration software must only set this bit if the Root Port Upstream from the Endpoint or Bridge reports an RCB value of 128 bytes (a value of 1b in the Read Completion Boundary bit).For functions that do not implement this feature, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 330x0R/WPCIE_CAP_LINK_DISABLEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr27997Link Disable.This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.Writes to this bit are immediately reflected in the value read from the bit, regardless of actual Link state.After clearing this bit, software must honor timing requirements defined in Section 6.6.1 with respect to the first Configuration Read following a Conventional Reset.In a DSP that supports crosslink, the controller gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF.Note: The access attributes of this field are as follows: - Wire: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1 ? RW : RO - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO 44R/WPCIE_CAP_RETRAIN_LINKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SETDWC_pcie_wire_cpcie_usp_4x8.csr28028Retrain Link.A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration, re-entering Recovery is permitted but not required. If the Port is in DPC when a write of 1b to this bit occurs, the result is undefined. Reads of this bit always return 0b.It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. If the LTSSM is not already in Recovery or Configuration, the resulting Link training must use the modified values. If the LTSSM is already in Recovery or Configuration, the modified values are not required to affect the Link training that's already in progress.This bit is not applicable and is Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.This bit always returns 0b when read.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description 55R/WPCIE_CAP_COMMON_CLK_CONFIGDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SETDWC_pcie_wire_cpcie_usp_4x8.csr28063Common Clock Configuration. When set, this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock.A value of 0b indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock.For non-ARI Multi-Function Devices, software must program the same value for this bit in all Functions. If not all Functions are Set, then the component must as a whole assume that its reference clock is not common with the Upstream component.For ARI Devices, Common Clock Configuration is determined solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.Components utilize this common clock configuration information to report the correct L0s and L1 Exit Latencies.After changing the value in this bit in both components on a Link, software must trigger the Link to retrain by writing a 1b to the Retrain Link bit of the Downstream Port.660x0R/WPCIE_CAP_EXTENDED_SYNCHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr28082Extended Synch. When set, this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI Express Base Specification). This mode provides external devices (for example, logic analyzers) monitoring the Link time to achieve bit and Symbol lock before the Link enters the L0 state and resumes communication.For Multi-Function devices if any function has this bit set, then the component must transmit the additional Ordered Sets when exiting L0s or when in Recovery.770x0R/WPCIE_CAP_EN_CLK_POWER_MANDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SETDWC_pcie_wire_cpcie_usp_4x8.csr28127Enable Clock Power Management.Applicable only for Upstream Ports and with form factors that support a "Clock Request" (CLKREQ#) mechanism, this bit operates as follows: - 0b: Clock power management is disabled and device must hold CLKREQ# signal low. - 1b: When this bit is set, the device is permitted to use CLKREQ# signal to power manage Link clock according to protocol defined in appropriate form factor specification.For a non-ARI Multi-Function Device, power-management-configuration software must only Set this bit if all Functions of the Multi-Function Device indicate a 1b in the Clock Power Management bit of the Link Capabilities register. The component is permitted to use the CLKREQ# signal to power manage Link clock only if this bit is Set for all Functions.For ARI Devices, Clock Power Management is enabled solely by the setting in Function 0. The settings in the other Functions always return whatever value software programmed for each, but otherwise are ignored by the component.The CLKREQ# signal may also be controlled via the L1 PM Substates mechanism. Such control is not affected by the setting of this bit.For Downstream Ports and components that do not support Clock Power Management (as indicated by a 0b value in the Clock Power Management bit of the Link Capabilities register), the controller hardwires this bit to 0b.The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG.Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS Note: This register field is sticky.88R/WPCIE_CAP_HW_AUTO_WIDTH_DISABLEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr28150Hardware Autonomous Width Disable.When set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RW, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.For components that do not implement the ability autonomously to change Link width, the ciontroller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 990x0R/WPCIE_CAP_LINK_BW_MAN_INT_ENDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr28175Link Bandwidth Management Interrupt Enable. When set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO 1010R/WPCIE_CAP_LINK_AUTO_BW_INT_ENDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr28200Link Autonomous Bandwidth Management Interrupt Enable.When set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO 1111R/WRSVDP_12DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr28208Reserved for future use.13120x0RPCIE_CAP_DRS_SIGNALING_CONTROLDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SETDWC_pcie_wire_cpcie_usp_4x8.csr28243DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b: DRS not ReportedIf DRS Supported is set, receiving a DRS Message will set DRS Message Received in the Link Status 2 Register but will otherwise have no effect - 01b: DRS Interrupt EnabledIf the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, and either MSI or MSI-X is enabled, an MSI or MSI-X interrupt is generated using the vector in Interrupt Message Number (section 7.5.3.2) - 10b: DRS to FRS Signaling EnabledIf the DRS Message Received bit in the Link Status 2 Register transitions from 0 to 1, the Port must send an FRS Message Upstream with the FRS Reason field set to DRS Message Received.Behavior is undefined if this field is set to 10b and the FRS Supported bit in the Device Capabilities 2 Register is Clear.Behavior is undefined if this field is set to 11b.For Downstream Ports with the DRS Supported bit clear in the Link Capabilities 2 register, the controller hardwires this field to 00b.This field is Reserved for Upstream Ports.15140x0RPCIE_CAP_LINK_SPEEDDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SETDWC_pcie_wire_cpcie_usp_4x8.csr28268Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the current Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are Reserved.The value in this field is undefined when the Link is not up.1916RPCIE_CAP_NEGO_LINK_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr28288Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link.Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32All other encodings are Reserved. The value in this field is undefined when the Link is not up.2520RRSVDP_26DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_SETDWC_pcie_wire_cpcie_usp_4x8.csr28296Reserved for future use.26260x0RPCIE_CAP_LINK_TRAININGDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SETDWC_pcie_wire_cpcie_usp_4x8.csr28317Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery state.This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches, and the controller hardwires it to 0b.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R 2727RPCIE_CAP_SLOT_CLK_CONFIGDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SETDWC_pcie_wire_cpcie_usp_4x8.csr28337Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a reference clock on the connector, this bit must be clear.For a Multi-Function Device, each Function must report the same value for this bit.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 28280x1RPCIE_CAP_DLL_ACTIVEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SETDWC_pcie_wire_cpcie_usp_4x8.csr28352Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise.This bit must be implemented if the Data Link Layer Link Active Reporting Capable bit is 1b. Otherwise, the controller hardwires it to 0b.29290x0RPCIE_CAP_LINK_BW_MAN_STATUSDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr28389Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of 1b to the Retrain Link bit.Note: This bit is set following any write of 1b to the Retrain Link bit, including when the Link is in the process of retraining for some other reason. - Hardware has changed Link speed or width to attempt to correct unreliable Link operation, either through an LTSSM timeout or a higher level process.This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was not indicated as an autonomous change.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.The default value of this bit is 0b.The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R 30300x0RPCIE_CAP_LINK_AUTO_BW_STATUSDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr28420Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation.This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was indicated as an autonomous change.The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.This bit is not applicable and is Reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches.For functions that do not implement the Link Bandwidth Notification Capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R 31310x0RregisterDBI_Slave.PF0_PCIE_CAP.DEVICE_CAPABILITIES2_REGDEVICE_CAPABILITIES2_REGDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_OFFSETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr286790x24R0x8001181fDBI_Slave_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REGDevice Capabilities 2 Register.falsefalsefalsefalsePCIE_CAP_CPL_TIMEOUT_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SETDWC_pcie_wire_cpcie_usp_4x8.csr28460Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value.This field is applicable only to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is Reserved and must be hardwired to 0000b.Four time value ranges are defined: - Range A: 50 us to 10 ms - Range B: 10 ms to 250 ms - Range C: 250 ms to 4 s - Range D: 4 s to 64 sBits are set according to the list below to show timeout value ranges supported. - 0000b Completion Timeout programming not supported – the Function must implement a timeout value in the range 50 μs to 50 ms. - 0001b Range A - 0010b Range B - 0011b Ranges A and B - 0110b Ranges B and C - 0111b Ranges A, B, and C - 1110b Ranges B, C, and D - 1111b Ranges A, B, C, and DAll other values are Reserved.It is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.300xfRPCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORTDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr28478Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism.The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own behalf and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express.This mechanism is optional for Root Ports.For all other Functions this field is Reserved and the controller hardwires this bit to 0b.440x1RPCIE_CAP_ARI_FORWARD_SUPPORTDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr28490ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability. For more details, see section 6.13 of PCI Express Base Specification.550x0RPCIE_CAP_ATOMIC_ROUTING_SUPPDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SETDWC_pcie_wire_cpcie_usp_4x8.csr28502AtomicOp Routing Supported. Applicable only to Switch Upstream Ports, Switch Downstream Ports, and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For more details, see section 6.15 of PCI Express Base Specification.660x0RPCIE_CAP_32_ATOMIC_CPL_SUPPDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SETDWC_pcie_wire_cpcie_usp_4x8.csr2851532-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability. For more details on additional RC requirements, see section 6.15.3.1 of PCI Express Base Specification.770x0RPCIE_CAP_64_ATOMIC_CPL_SUPPDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SETDWC_pcie_wire_cpcie_usp_4x8.csr2852864-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability. For more details on additional RC requirements, see section 6.15.3.1 of PCI Express Base Specification.880x0RPCIE_CAP_128_CAS_CPL_SUPPDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SETDWC_pcie_wire_cpcie_usp_4x8.csr28539128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details, see section 6.15 of PCI Express Base Specification.990x0RPCIE_CAP_NO_RO_EN_PR2PR_PARDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SETDWC_pcie_wire_cpcie_usp_4x8.csr28557No RO-enabled PR-PR Passing. If this bit is set, the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute field being Set.This bit applies only for Switches and RCs that support peer-to-peer traffic between Root Ports. This bit applies only to Posted Requests being forwarded through the Switch or RC and does not apply to traffic originating or terminating within the Switch or RC itself. All Ports on a Switch or RC must report the same value for this bit.For all other functions, this bit must be 0b.10100x0RPCIE_CAP_LTR_SUPPDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SETDWC_pcie_wire_cpcie_usp_4x8.csr28580LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism.Root Ports, Switches and Endpoints are permitted to implement this capability.For a Multi-Function Device associated with an Upstream Port, each Function must report the same value for this bit.For Bridges and other Functions that do not implement this capability, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(Sticky) else R(Sticky) Note: This register field is sticky.11110x1RPCIE_CAP_TPH_CMPLT_SUPPORT_0DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr28599TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions, this field is Reserved.Defined Encodings are: - 00b: TPH and Extended TPH Completer not supported. - 01b: TPH Completer supported; Extended TPH Completer not supported. - 10b: Reserved. - 11b: Both TPH and Extended TPH Completer supported.For more details, see section 6.17 of PCI Express Base Specification.12120x1RPCIE_CAP_TPH_CMPLT_SUPPORT_1DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr28606TPH Completer Supported Bit 1.13130x0RPCIE_CAP2_LN_SYS_CLSDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_SETDWC_pcie_wire_cpcie_usp_4x8.csr28623LN System CLS. Applicable only to Root Ports and RCRBs; must be 00b for all other Function types. This field indicates if the Root Port or RCRB supports LN protocol as an LN Completer, and if so, what cacheline size is in effect.Encodings are: - 00b LN Completer either not supported or not in effect - 01b LN Completer with 64-byte cachelines in effect - 10b LN Completer with 128-byte cachelines in effect - 11b ReservedNote: This register field is sticky.15140x0RPCIE_CAP2_10_BIT_TAG_COMP_SUPPORTDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr2863310-Bit Tag Completer Supported. If this bit is set, the Function supports 10-Bit Tag Completer capability; otherwise, the Function does not. For more details, see section 2.2.6.2. of PCI Express Base Specification.16160x1RPCIE_CAP2_10_BIT_TAG_REQ_SUPPORTDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr2865110-Bit Tag Requester Supported. If this bit is set, the Function supports 10-Bit Tag Requester capability; otherwise, the Function does not.This bit must not be set if the 10-Bit Tag Completer Supported bit is clear.Note: 10-Bit Tag field generation must be enabled by the 10-Bit Tag Requester Enable bit in the Device Control 2 register of the Requester Function before 10-Bit Tags can be generated by the Requester. For more details, see section 2.2.6.2. of PCI Express Base Specification.17170x0R--23180x0rRSVDP_24DBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr28658Reserved for future use.30240x00RPCIE_CAP_FRS_SUPPORTEDDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_FRS_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr28678FRS Supported. When set, indicates support for the optional Function Readiness Status (FRS) capability.Must be set for all Functions that support generation or reception capabilities of FRS Messages.Must not be set by Switch Functions that do not generate FRS Messages on their own behalf.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 31310x1RregisterDBI_Slave.PF0_PCIE_CAP.DEVICE_CONTROL2_DEVICE_STATUS2_REGDEVICE_CONTROL2_DEVICE_STATUS2_REGDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_OFFSETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr288090x28R/W0x00000000DBI_Slave_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REGDevice Control 2 and Status 2 Register.falsefalsefalsefalsePCIE_CAP_CPL_TIMEOUT_VALUEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr28737Completion Timeout Value. In device Functions that support Completion Timeout programmability, this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is Reserved and controller hardwires it to 0000b.A Function that does not support this optional capability must hardwire this field to 0000b and is required to implement a timeout value in the range 50 μs to 50 ms. Functions that support Completion Timeout programmability must support the values given below corresponding to the programmability ranges indicated in the Completion Timeout Ranges Supported field.Defined encodings: - 0000b Default range: 50 μs to 50 msIt is strongly recommended that the Completion Timeout mechanism not expire in less than 10 ms.Values available if Range A (50 μs to 10 ms) programmability range is supported: - 0001b: 50 μs to 100 μs - 0010b: 1 ms to 10 msValues available if Range B (10 ms to 250 ms) programmability range is supported: - 0101b 16 ms to 55 ms - 0110b 65 ms to 210 msValues available if Range C (250 ms to 4 s) programmability range is supported: - 1001b 260 ms to 900 ms - 1010b 1 s to 3.5 sValues available if the Range D (4 s to 64 s) programmability range is supported: - 1101b 4 s to 13 s - 1110b 17 s to 64 sValues not defined above are Reserved.Software is permitted to change the value in this field at any time. For Requests already pending when the Completion Timeout Value is changed, hardware is permitted to use either the new or the old value for the outstanding Requests, and is permitted to base the start time for each Request either on when this value was changed or on when each request was issued.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 300x0R/WPCIE_CAP_CPL_TIMEOUT_DISABLEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr28758Completion Timeout Disable. When set, this bit disables the Completion Timeout mechanism.This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this optional capability are permitted to hardwire this bit to 0bSoftware is permitted to set or clear this bit at any time. When set, the Completion Timeout detection mechanism is disabled. If there are outstanding Requests when the bit is cleared, it is permitted but not required for hardware to apply the completion timeout mechanism to the outstanding Requests. If this is done, it is permitted to base the start time for each Request on either the time this bit was cleared or the time each Request was issued.440x0R/WPCIE_CAP_ARI_FORWARD_SUPPORT_CSDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SETDWC_pcie_wire_cpcie_usp_4x8.csr28772ARI Forwarding Enable. When set, the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request, permitting access to Extended Functions in an ARI Device immediately below the Port. For more details, see Section 6.13 of PCI Express Base Specification.550x0R--960x0rPCIE_CAP_LTR_ENDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_WIDTHDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_MSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_LSBDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_RANGEDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_RESETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_GETDBI_SLAVE_PF0_PCIE_CAP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr28808LTR Mechanism Enable. When set to 1b, this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages.For a Multi-Function Device associated with an Upstream Port of a device that implements LTR, the bit in Function 0 is RW, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is RsvdP.Functions that do not implement the LTR mechanism are permitted to hardwire this bit to 0b.For Downstream Ports, this bit must be reset to the default value if the Port goes to DL_Down status.The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG.Note: RW for function #0 and RsdvP for all other functions.Note: The access attributes of this field are as follows: - Wire: if (pf=0 && DEVICE_CAPABILITIES2_REG.PCIE_CAP_LTR_SUPP) then R/W else R - Dbi: if (pf=0 && DEVICE_CAPABILITIES2_REG.PCIE_CAP_LTR_SUPP) then R/W else R 10100x0R/W--31110x0rregisterDBI_Slave.PF0_PCIE_CAP.LINK_CAPABILITIES2_REGLINK_CAPABILITIES2_REGDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_OFFSETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr289700x2CR0x81800000DBI_Slave_PF0_PCIE_CAP_LINK_CAPABILITIES2_REGLink Capabilities 2 Register.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr28820Reserved for future use.000x0RPCIE_CAP_SUPPORT_LINK_SPEED_VECTORDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr28850Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit, a value of 1b indicates that the corresponding Link speed is supported; otherwise, the Link speed is not supported. For more details, see section 8.2.1 of PCI Express Base Specification.Bit definitions within this field are: - Bit 0 2.5 GT/s - Bit 1 5.0 GT/s - Bit 2 8.0 GT/s - Bit 3 16.0 GT/s - Bit 4 32.0 GT/s - Bits 6:5 RsvdPMulti-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0101) ? 0011111 : (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register.71RPCIE_CAP_CROSS_LINK_SUPPORTDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr28878Crosslink Supported. When set to 1b, this bit indicates that the associated Port supports crosslinks (for more details, see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link speeds of 8.0 GT/s or higher, this bit indicates that the associated Port does not support crosslinks. When set to 0b on a Port that only supports Link speeds of 2.5 GT/s or 5.0 GT/s, this bit provides no information regarding the Port’s level of crosslink support.It is recommended that this bit be Set in any Port that supports crosslinks even though doing so is only required for Ports that also support operating at 8.0 GT/s or higher Link speeds.Note: Software should use this bit when referencing fields whose definition depends on whether or not the Port supports crosslinks (for more details, see section 7.7.3.4 of PCI Express Base Specification).Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.880x0RRSVDP_9DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr28885Reserved for future use.2290x0000RPCIE_CAP_RETIMER_PRE_DET_SUPPORTDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_RETIMER_PRE_DET_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr28910Retimer Presence Detect Supported. When set to 1b, this bit indicates that the associated Port supports detection and reporting of Retimer presence.This bit must be set to 1b in a Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher.It is permitted to be set to 1b regardless of the supported Link speeds.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 23230x1RPCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORTDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr28937Two Retimers Presence Detect Supported. When set to 1b, this bit indicates that the associated Port supports detection and reporting of two Retimers presence.This bit must be set to 1b in a Port when the Supported Link Speeds Vector of the Link Capabilities 2 register indicates support for a Link speed of 16.0 GT/s or higher.It is permitted to be set to 1b regardless of the supported Link speeds if the Retimer Presence Detect Supported bit is also set to 1b.Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 24240x1RRSVDP_25DBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_RSVDP_25_SETDWC_pcie_wire_cpcie_usp_4x8.csr28944Reserved for future use.30250x00RDRS_SUPPORTEDDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr28969DRS Supported. When set, indicates support for the optional Device Readiness Status (DRS) capability.Must be Set in Downstream Ports that support DRS.Must be Set in Downstream Ports that support FRS.For Upstream Ports that support DRS, it is strongly recommended that this bit be Set in Function 0. For all other Functions associated with an Upstream Port, this bit must be Clear.127Must be Clear in Functions that are not associated with a Port.RsvdP in all other Functions.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R 31310x1RregisterDBI_Slave.PF0_PCIE_CAP.LINK_CONTROL2_LINK_STATUS2_REGLINK_CONTROL2_LINK_STATUS2_REGDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_OFFSETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr294960x30R/W0x00010000DBI_Slave_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REGLink Control 2 and Status 2 Register.falsefalsefalsefalsePCIE_CAP_TARGET_LINK_SPEEDDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SETDWC_pcie_wire_cpcie_usp_4x8.csr29034Target Link Speed. For Downstream Ports, this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences.The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the desired target Link speed.Defined encodings are: - 0001b: Supported Link Speeds Vector field bit 0 - 0010b: Supported Link Speeds Vector field bit 1 - 0011b: Supported Link Speeds Vector field bit 2 - 0100b: Supported Link Speeds Vector field bit 3 - 0101b: Supported Link Speeds Vector field bit 4 - 0110b: Supported Link Speeds Vector field bit 5 - 0111b: Supported Link Speeds Vector field bit 6All other encodings are Reserved.If a value is written to this field that does not correspond to a supported speed (as indicated by the Supported Link Speeds Vector), the result is undefined.If either of the Enter Compliance or Enter Modified Compliance bits are implemented, then this field must also be implemented.The default value of this field is the highest Link speed supported by the component (as reported in the Max Link Speed field of the Link Capabilities register) unless the corresponding platform/form factor requires a different default value.For both Upstream and Downstream Ports, this field is used to set the target compliance mode speed when software is using the Enter Compliance bit to force a Link into compliance mode.For Upstream Ports, if the Enter Compliance bit is Clear, this field is permitted to have no effect.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.Components that support only the 2.5 GT/s speed are permitted to hardwire this field to 0000b.For a description of this standard PCIe register field, see the PCI Express Base Specification. In M-PCIe mode, the contents of this field are derived from other registers.Note: This register field is sticky.30R/WPCIE_CAP_ENTER_COMPLIANCEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr29067Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by setting this bit to 1b in both components on a Link and then initiating a hot reset on the Link.Default value of this bit following Fundamental Reset is 0b.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this bit is of type RsvdP.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.Note: This register field is sticky.440x0R/WPCIE_CAP_HW_AUTO_SPEED_DISABLEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr29092Hardware Autonomous Speed Disable. When set, this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial transition to the highest supported common link speed is not blocked by this bit.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.Functions that do not implement the associated mechanism are permitted to hardwire this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.550x0R/WPCIE_CAP_SEL_DEEMPHASISDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29117Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed, this bit is used to control the transmit de-emphasis of the link in specific situations. For more details, see section 4.2.6 of PCI Express Base Specification.Encodings: - 1b: -3.5 dB - 0b: -6 dBWhen the Link is not operating at 5.0 GT/s speed, the setting of this bit has no effect. Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.This bit is not applicable and Reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.Note: This register field is sticky.660x0RPCIE_CAP_TX_MARGINDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SETDWC_pcie_wire_cpcie_usp_4x8.csr29151Transmit Margin – This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base Specification for details of how the Transmitter voltage level is determined in various states).Encodings: - 000b: Normal operating range - 001b-111b: As defined in Section 8.3.4 not all encodings are required to be implemented.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this field is of type RsvdP.For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 000b.This field is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.Note: This register field is sticky.970x0R/WPCIE_CAP_ENTER_MODIFIED_COMPLIANCEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr29178Enter Modified Compliance. When this bit is set to 1b, the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this bit is of type RsvdP.This bit is intended for debug, compliance testing purposes only. System firmware and software is allowed to modify this bit only during debug or compliance testing. In all other cases, the system must ensure that this bit is set to the default value.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.10100x0R/WPCIE_CAP_COMPLIANCE_SOSDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29205Compliance SOS. When set to 1b, the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern.For a Multi-Function Device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other Functions of that device, this bit is of type RsvdP.This bit is applicable when the Link is operating at 2.5 GT/s or 5.0 GT/s data rates only.For components that support only the 2.5 GT/s speed, the controller hardwires this bit to 0b.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.11110x0R/WPCIE_CAP_COMPLIANCE_PRESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SETDWC_pcie_wire_cpcie_usp_4x8.csr29247Compliance Preset/De-emphasis.For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in section 4.2.3.2 of PCI Express Base Specification . Results are undefined if a reserved preset encoding is used when entering Polling.Compliance in this way.For 5.0 GT/s Data Rate: This field sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.Defined Encodings are: - 0001b: -3.5 dB - 0000b: -6 dBWhen the Link is operating at 2.5 GT/s, the setting of this field has no effect. Components that support only 2.5 GT/s speed are permitted to hardwire this field to 0000b.For a Multi-Function Device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component's Link behavior. In all other Functions of that device, this field is of type RsvdP.This field is intended for debug and compliance testing purposes. System firmware and software is allowed to modify this field only during debug or compliance testing. In all other cases, the system must ensure that this field is set to the default value.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.15120x0R/WPCIE_CAP_CURR_DEEMPHASISDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29273Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed, this bit reflects the level of de-emphasis.Encodings: - 1b: -3.5 dB - 0b: -6 dBThe value in this bit is undefined when the Link is not operating at 5.0 GT/s speed.Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to 0b.For components that support speeds greater than 2.5 GT/s, Multi-Function Devices associated with an Upstream Port must report the same value in this field for all Functions of the Port. In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE.16160x1RPCIE_CAP_EQ_CPLDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_SETDWC_pcie_wire_cpcie_usp_4x8.csr29295Equalization 8.0 GT/s Complete. When set to 1b, this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.17170x0RPCIE_CAP_EQ_CPL_P1DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_SETDWC_pcie_wire_cpcie_usp_4x8.csr29317Equalization 8.0 GT/s Phase 1 Successful. When set to 1b, this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.18180x0RPCIE_CAP_EQ_CPL_P2DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_SETDWC_pcie_wire_cpcie_usp_4x8.csr29339Equalization 8.0 GT/s Phase 2 Successful. When set to 1b, this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.19190x0RPCIE_CAP_EQ_CPL_P3DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_SETDWC_pcie_wire_cpcie_usp_4x8.csr29361EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b, this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit needs to be set to 1b is provided in section 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.Note: This register field is sticky.20200x0RPCIE_CAP_LINK_EQ_REQDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr29379Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details, see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification.For Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions. For components that only support speeds below 8.0 GT/s, the controller hardwires this bit to 0b.21210x0R/W1CPCIE_CAP_RETIMER_PRE_DETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_RETIMER_PRE_DET_SETDWC_pcie_wire_cpcie_usp_4x8.csr29405Retimer Presence Detected. When set to 1b, this bit indicates that a Retimer was present during the most recent Link negotiation. For more details, see section 4.2.6.3.5.1 of PCI Express Base Specification.This bit is required for Ports that have the Retimer Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.For Ports that have the Retimer Presence Detect Supported bit set to 0b, the controller hardwires this bit to 0b.For Multi-Function Devices associated with an Upstream Port, this bit must be implemented in Function 0 and is RsvdZ in all other Functions.Note: This register field is sticky.22220x0RPCIE_CAP_TWO_RETIMERS_PRE_DETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TWO_RETIMERS_PRE_DET_SETDWC_pcie_wire_cpcie_usp_4x8.csr29431Two Retimers Presence Detected. When set to 1b, this bit indicates that two Retimers were present during the most recent Link negotiation. For more details, see section 4.2.6.3.5.1 of PCI Express Base Specification.This bit is required for Ports that have the Two Retimers Presence Detect Supported bit of the Link Capabilities 2 register set to 1b.Ports that have the Two Retimers Presence Detect Supported bit set to 0b are permitted to hardwire this bit to 0b.For Multi-Function Devices associated with an Upstream Port, this bit must be implemented in Function 0 and RsvdZ in all other Functions.Note: This register field is sticky.23230x0R--25240x0rRSVDP_26DBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_SETDWC_pcie_wire_cpcie_usp_4x8.csr29439Reserved for future use.27260x0RDOWNSTREAM_COMPO_PRESENCEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr29479Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component, if any, connected to the Link; defined values are: - 000b: Link Down – Presence Not Determined - 001b: Link Down – Component Not Present indicates the Downstream Port (DP) has determined that a Downstream Component is not present - 010b: Link Down – Component Present indicates the DP has determined that a Downstream Component is present, but the Data Link Layer is not active - 011b: Reserved - 100b: Link Up – Component Presentindicates the DP has determined that a Downstream Component is present, but no DRS Message has been received since the Data Link Layer became active - 101b: Link Up – Component Present and DRS Received indicates the DP has received a DRS Message since the Data Link Layer became active - 110b: Reserved - 111b: ReservedComponent Presence state must be determined by the logical "OR" of the Physical Layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism implemented for the Link. If no out-of-band presence detect mechanism is implemented, then Component Presence state must be determined solely by the Physical Layer in-band presence detect mechanism.This field must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities 2 register.This field is RsvdZ for all other Functions.30280x0RDRS_MESSAGE_RECEIVEDDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_WIDTHDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_MSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_LSBDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_RANGEDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_RESETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_FIELD_MASKDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_GETDBI_SLAVE_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_SETDWC_pcie_wire_cpcie_usp_4x8.csr29495DRS Message Received. This bit must be set whenever the Port receives a DRS Message.This bit must be cleared in DL_Down.This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities 2 register.This bit is RsvdZ for all other Functions.31310x0RgroupDBI_Slave.PF0_MSIX_CAPPF0_MSIX_CAPDBI_SLAVE_PF0_MSIX_CAP_ADDRESSDBI_SLAVE_PF0_MSIX_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_MSIX_CAP_OFFSETDBI_SLAVE_PF0_MSIX_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr296990xB0R/WDBI_Slave_PF0_MSIX_CAPPF MSI-X Capability StructureregisterDBI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGregisterDBI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGregisterDBI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGregisterDBI_Slave.PF0_MSIX_CAP.PCI_MSIX_CAP_ID_NEXT_CTRL_REGPCI_MSIX_CAP_ID_NEXT_CTRL_REGDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_ADDRESSDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_OFFSETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr295880x0R/W0x00800011DBI_Slave_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REGMSI-X Capability ID, Next Pointer, Control Registers.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_CAP_IDDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_WIDTHDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_MSBDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_LSBDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_RANGEDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_RESETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_GETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr29516MSI-X Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x11RPCI_MSIX_CAP_NEXT_OFFSETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_MSBDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_LSBDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_RESETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_GETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr29532MSI-X Next Capability Pointer.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.1580x00RPCI_MSIX_TABLE_SIZEDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_WIDTHDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_MSBDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_LSBDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RANGEDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_RESETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_FIELD_MASKDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_GETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr29557MSI-X Table Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26160x080RRSVDP_27DBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_WIDTHDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MSBDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_LSBDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RANGEDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_RESETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_GETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr29565Reserved for future use.29270x0RPCI_MSIX_FUNCTION_MASKDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_WIDTHDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_MSBDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_LSBDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_RANGEDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_RESETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_FIELD_MASKDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_GETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr29578Function Mask.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 30300x0R/WPCI_MSIX_ENABLEDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_WIDTHDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_MSBDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_LSBDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_RANGEDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_RESETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_FIELD_MASKDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_GETDBI_SLAVE_PF0_MSIX_CAP_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr29587MSI-X Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterDBI_Slave.PF0_MSIX_CAP.MSIX_TABLE_OFFSET_REGMSIX_TABLE_OFFSET_REGDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_ADDRESSDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_OFFSETDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr296430x4R0x00000004DBI_Slave_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REGMSI-X Table Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_BIRDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_WIDTHDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_MSBDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_LSBDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RANGEDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_RESETDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_FIELD_MASKDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_GETDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_SETDWC_pcie_wire_cpcie_usp_4x8.csr29618MSI-X Table BAR Indicator Register Field.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table BAR Indicator Register" (PCI_MSIX_BIR field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_BIR field in the PF MSIX_TABLE_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x4RPCI_MSIX_TABLE_OFFSETDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_WIDTHDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_MSBDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_LSBDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RANGEDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_RESETDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_FIELD_MASKDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_GETDBI_SLAVE_PF0_MSIX_CAP_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr29642MSI-X Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Offset" (PCI_MSIX_TABLE_OFFSET field in SHADOW_MSIX_TABLE_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_OFFSET field in the PF MSIX_TABLE_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3130x00000000RregisterDBI_Slave.PF0_MSIX_CAP.MSIX_PBA_OFFSET_REGMSIX_PBA_OFFSET_REGDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_ADDRESSDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_OFFSETDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr296980x8R0x00008004DBI_Slave_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REGMSI-X PBA Offset and BIR Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCI_MSIX_PBA_BIRDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_WIDTHDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_MSBDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_LSBDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RANGEDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_RESETDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_FIELD_MASKDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_GETDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_BIR_SETDWC_pcie_wire_cpcie_usp_4x8.csr29673MSI-X PBA BIR.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA BIR" (PCI_MSIX_PBA_BIR field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_BIR field in the PF MSIX_PBA_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.200x4RPCI_MSIX_PBA_OFFSETDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_WIDTHDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_MSBDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_LSBDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RANGEDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_RESETDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_FIELD_MASKDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_GETDBI_SLAVE_PF0_MSIX_CAP_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr29697MSI-X PBA Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same value for "MSI-X PBA Offset" (PCI_MSIX_PBA_OFFSET field in SHADOW_MSIX_PBA_OFFSET_REG). To write this common value, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_PBA_OFFSET field in the PF MSIX_PBA_OFFSET_REG register.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.3130x00001000RgroupDBI_Slave.PF0_AER_CAPPF0_AER_CAPDBI_SLAVE_PF0_AER_CAP_ADDRESSDBI_SLAVE_PF0_AER_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_OFFSETDBI_SLAVE_PF0_AER_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr311200x100R/WDBI_Slave_PF0_AER_CAPPF Advanced Error Reporting Capability StructureregisterDBI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFregisterDBI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFregisterDBI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFregisterDBI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFregisterDBI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFregisterDBI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFregisterDBI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFregisterDBI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFregisterDBI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFregisterDBI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFregisterDBI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFregisterDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFregisterDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFregisterDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFregisterDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFregisterDBI_Slave.PF0_AER_CAP.AER_EXT_CAP_HDR_OFFAER_EXT_CAP_HDR_OFFDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr297580x0R0x14820001DBI_Slave_PF0_AER_CAP_AER_EXT_CAP_HDR_OFFAdvanced Error Reporting Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCAP_IDDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_WIDTHDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_MSBDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_LSBDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_RANGEDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_RESETDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_GETDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr29725AER Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0001RCAP_VERSIONDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_WIDTHDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MSBDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_LSBDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_RANGEDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_RESETDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_GETDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr29741Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x2RNEXT_OFFSETDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MSBDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_LSBDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_RESETDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_GETDBI_SLAVE_PF0_AER_CAP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr29757Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x148RregisterDBI_Slave.PF0_AER_CAP.UNCORR_ERR_STATUS_OFFUNCORR_ERR_STATUS_OFFDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr299340x4R/W0x00000000DBI_Slave_PF0_AER_CAP_UNCORR_ERR_STATUS_OFFUncorrectable Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr29771Reserved for future use.300x0RDL_PROTOCOL_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29781Data Link Protocol Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.44R/W1CSURPRISE_DOWN_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29791Surprise Down Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.55R/W1CRSVDP_6DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr29799Reserved for future use.1160x00RPOIS_TLP_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29810Poisoned TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0R/W1CFC_PROTOCOL_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29820Flow Control Protocol Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.1313R/W1CCMPLT_TIMEOUT_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29831Completion Timeout Status.For a description of this standard PCIe register field, see the PCI Express Specification.14140x0R/W1CCMPLT_ABORT_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29842Completer Abort Status.For a description of this standard PCIe register field, see the PCI Express Specification.15150x0R/W1CUNEXP_CMPLT_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29853Unexpected Completion Status.For a description of this standard PCIe register field, see the PCI Express Specification.16160x0R/W1CREC_OVERFLOW_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29863Receiver Overflow Status.For a description of this standard PCIe register field, see the PCI Express Specification.1717R/W1CMALF_TLP_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29873Malformed TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.1818R/W1CECRC_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29887ECRC Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.Note:If CX_ECRC_ENABLE=0 the register field always reads 0.19190x0R/W1CUNSUPPORTED_REQ_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29898Unsupported Request Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.20200x0R/W1C--21210x0rINTERNAL_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr29917Uncorrectable Internal Error Status.For a description of this standard PCIe register field, see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it detects internal uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these errors to drive the app_err_bus[9] input. For more details, see the "Data Integrity (Wire, Datapath, and RAM Protection)" section in the Databook.22220x0R/W1CRSVDP_23DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr29925Reserved for future use.23230x0R--26240x0rRSVDP_27DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_STATUS_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr29933Reserved for future use.31270x00RregisterDBI_Slave.PF0_AER_CAP.UNCORR_ERR_MASK_OFFUNCORR_ERR_MASK_OFFDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr301430x8R/W0x00400000DBI_Slave_PF0_AER_CAP_UNCORR_ERR_MASK_OFFUncorrectable Error Mask Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr29947Reserved for future use.300x0RDL_PROTOCOL_ERR_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr29958Data Link Protocol Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.440x0R/WSURPRISE_DOWN_ERR_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr29970Surprise Down Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x0RRSVDP_6DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr29978Reserved for future use.1160x00RPOIS_TLP_ERR_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr29989Poisoned TLP Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WFC_PROTOCOL_ERR_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30000Flow Control Protocol Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x0R/WCMPLT_TIMEOUT_ERR_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30011Completion Timeout Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x0R/WCMPLT_ABORT_ERR_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30022Completer Abort Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x0R/WUNEXP_CMPLT_ERR_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30033Unexpected Completion Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.16160x0R/WREC_OVERFLOW_ERR_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30044Receiver Overflow Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.17170x0R/WMALF_TLP_ERR_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30055Malformed TLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.18180x0R/WECRC_ERR_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30069ECRC Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WUNSUPPORTED_REQ_ERR_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30080Unsupported Request Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.20200x0R/WACS_VIOLATION_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ACS_VIOLATION_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30103ACS Violation Mask.Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors.The bit is Read-Only Zero for upstream ports, when ACS P2P Egress Control Enable is not set.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: if (acs_viol_svrity_mask_wr_en == 1) then R/W (Sticky) else R(Sticky) - Dbi: if (acs_viol_svrity_mask_wr_en == 1) then R/W (Sticky) else R(Sticky) Note: This register field is sticky.21210x0RINTERNAL_ERR_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30114Uncorrectable Internal Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.22220x1R/WRSVDP_23DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr30122Reserved for future use.23230x0RATOMIC_EGRESS_BLOCKED_ERR_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30134AtomicOp Egress Block Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.24240x0R--26250x0rRSVDP_27DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_MASK_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr30142Reserved for future use.31270x00RregisterDBI_Slave.PF0_AER_CAP.UNCORR_ERR_SEV_OFFUNCORR_ERR_SEV_OFFDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr303320xCR/W0x00462030DBI_Slave_PF0_AER_CAP_UNCORR_ERR_SEV_OFFUncorrectable Error Severity Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr30156Reserved for future use.300x0RDL_PROTOCOL_ERR_SEVERITYDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr30167Data Link Protocol Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.440x1R/WSURPRISE_DOWN_ERR_SVRITYDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr30179Surprise Down Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x1RRSVDP_6DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr30187Reserved for future use.1160x00RPOIS_TLP_ERR_SEVERITYDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr30198Poisoned TLP Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WFC_PROTOCOL_ERR_SEVERITYDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr30209Flow Control Protocol Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x1R/WCMPLT_TIMEOUT_ERR_SEVERITYDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr30220Completion Timeout Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x0R/WCMPLT_ABORT_ERR_SEVERITYDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr30231Completer Abort Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x0R/WUNEXP_CMPLT_ERR_SEVERITYDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr30242Unexpected Completion Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.16160x0R/WREC_OVERFLOW_ERR_SEVERITYDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr30253Receiver Overflow Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.17170x1R/WMALF_TLP_ERR_SEVERITYDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr30264Malformed TLP Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.18180x1R/WECRC_ERR_SEVERITYDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr30278ECRC Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WUNSUPPORTED_REQ_ERR_SEVERITYDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr30289Unsupported Request Error Severity.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.20200x0R/W--21210x0rINTERNAL_ERR_SEVERITYDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr30300Uncorrectable Internal Error Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.22220x1R/WRSVDP_23DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr30308Reserved for future use.23230x0RATOMIC_EGRESS_BLOCKED_ERR_SEVERITYDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr30323AtomicOp Egress Blocked Severity (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.24240x0R--26250x0rRSVDP_27DBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_WIDTHDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_MSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_LSBDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_RANGEDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_RESETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_GETDBI_SLAVE_PF0_AER_CAP_UNCORR_ERR_SEV_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr30331Reserved for future use.31270x00RregisterDBI_Slave.PF0_AER_CAP.CORR_ERR_STATUS_OFFCORR_ERR_STATUS_OFFDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr304500x10R/W0x00000000DBI_Slave_PF0_AER_CAP_CORR_ERR_STATUS_OFFCorrectable Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRX_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr30348Receiver Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.000x0R/W1CRSVDP_1DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr30356Reserved for future use.510x00RBAD_TLP_STATUSDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr30367Bad TLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.660x0R/W1CBAD_DLLP_STATUSDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr30378Bad DLLP Status.For a description of this standard PCIe register field, see the PCI Express Specification.770x0R/W1CREPLAY_NO_ROLEOVER_STATUSDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr30389REPLAY_NUM Rollover Status.For a description of this standard PCIe register field, see the PCI Express Specification.880x0R/W1CRSVDP_9DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr30397Reserved for future use.1190x0RRPL_TIMER_TIMEOUT_STATUSDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr30408Replay Timer Timeout Status.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0R/W1CADVISORY_NON_FATAL_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr30419Advisory Non-Fatal Error Status.For a description of this standard PCIe register field, see the PCI Express Specification.13130x0R/W1CCORRECTED_INT_ERR_STATUSDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr30430Corrected Internal Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.14140x0R/W1CHEADER_LOG_OVERFLOW_STATUSDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr30441Header Log Overflow Error Status (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.15150x0R/W1CRSVDP_16DBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_STATUS_OFF_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr30449Reserved for future use.31160x0000RregisterDBI_Slave.PF0_AER_CAP.CORR_ERR_MASK_OFFCORR_ERR_MASK_OFFDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr305680x14R/W0x0000e000DBI_Slave_PF0_AER_CAP_CORR_ERR_MASK_OFFCorrectable Error Mask Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRX_ERR_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RX_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30466Receiver Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.000x0R/WRSVDP_1DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr30474Reserved for future use.510x00RBAD_TLP_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30485Bad TLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.660x0R/WBAD_DLLP_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30496Bad DLLP Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.770x0R/WREPLAY_NO_ROLEOVER_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30507REPLAY_NUM Rollover Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.880x0R/WRSVDP_9DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr30515Reserved for future use.1190x0RRPL_TIMER_TIMEOUT_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30526Replay Timer Timeout Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.12120x0R/WADVISORY_NON_FATAL_ERR_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30537Advisory Non-Fatal Error Mask.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.13130x1R/WCORRECTED_INT_ERR_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30548Corrected Internal Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.14140x1R/WHEADER_LOG_OVERFLOW_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr30559Header Log Overflow Error Mask (Optional).For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.15150x1R/WRSVDP_16DBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_WIDTHDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_MSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_LSBDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_RANGEDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_RESETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_GETDBI_SLAVE_PF0_AER_CAP_CORR_ERR_MASK_OFF_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr30567Reserved for future use.31160x0000RregisterDBI_Slave.PF0_AER_CAP.ADV_ERR_CAP_CTRL_OFFADV_ERR_CAP_CTRL_OFFDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr306790x18R/W0x000000a0DBI_Slave_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFFAdvanced Error Capabilities and Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFIRST_ERR_POINTERDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_WIDTHDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_LSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_RANGEDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_RESETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_GETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr30587First Error Pointer.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.400x00RECRC_GEN_CAPDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_WIDTHDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_LSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_RANGEDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_RESETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_GETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr30599ECRC Generation Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.550x1RECRC_GEN_ENDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_WIDTHDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_LSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_RANGEDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_RESETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_GETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr30610ECRC Generation Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.660x0R/WECRC_CHECK_CAPDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_WIDTHDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_LSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_RANGEDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_RESETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_GETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr30622ECRC Check Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.770x1RECRC_CHECK_ENDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_WIDTHDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_LSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_RANGEDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_RESETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_GETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr30633ECRC Check Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.880x0R/WMULTIPLE_HEADER_CAPDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_WIDTHDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_LSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_RANGEDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_RESETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_GETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr30645Multiple Header Recording Capable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.990x0RMULTIPLE_HEADER_ENDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_WIDTHDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_LSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_RANGEDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_RESETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_GETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr30660Multiple Header Recording Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.10100x0R--11110x0rCTO_PRFX_HDR_LOG_CAPDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_WIDTHDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_MSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_LSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_RANGEDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_RESETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_GETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr30670TLP Prefix Log Present.For a description of this standard PCIe register field, see the PCI Express Specification.12120x0RRSVDP_13DBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_WIDTHDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_MSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_LSBDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_RANGEDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_RESETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_GETDBI_SLAVE_PF0_AER_CAP_ADV_ERR_CAP_CTRL_OFF_RSVDP_13_SETDWC_pcie_wire_cpcie_usp_4x8.csr30678Reserved for future use.31130x00000RregisterDBI_Slave.PF0_AER_CAP.HDR_LOG_0_OFFHDR_LOG_0_OFFDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr307380x1CR0x00000000DBI_Slave_PF0_AER_CAP_HDR_LOG_0_OFFHeader Log Register 0.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFIRST_DWORD_FIRST_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30698Byte 0 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RFIRST_DWORD_SECOND_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30711Byte 1 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RFIRST_DWORD_THIRD_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30724Byte 2 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RFIRST_DWORD_FOURTH_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30737Byte 3 of Header log register of First 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterDBI_Slave.PF0_AER_CAP.HDR_LOG_1_OFFHDR_LOG_1_OFFDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr307970x20R0x00000000DBI_Slave_PF0_AER_CAP_HDR_LOG_1_OFFHeader Log Register 1.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseSECOND_DWORD_FIRST_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30757Byte 0 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RSECOND_DWORD_SECOND_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30770Byte 1 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RSECOND_DWORD_THIRD_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30783Byte 2 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RSECOND_DWORD_FOURTH_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30796Byte 3 of Header log register of Second 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterDBI_Slave.PF0_AER_CAP.HDR_LOG_2_OFFHDR_LOG_2_OFFDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr308560x24R0x00000000DBI_Slave_PF0_AER_CAP_HDR_LOG_2_OFFHeader Log Register 2.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseTHIRD_DWORD_FIRST_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30816Byte 0 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RTHIRD_DWORD_SECOND_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30829Byte 1 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RTHIRD_DWORD_THIRD_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30842Byte 2 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RTHIRD_DWORD_FOURTH_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30855Byte 3 of Header log register of Third 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterDBI_Slave.PF0_AER_CAP.HDR_LOG_3_OFFHDR_LOG_3_OFFDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr309150x28R0x00000000DBI_Slave_PF0_AER_CAP_HDR_LOG_3_OFFHeader Log Register 3.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseFOURTH_DWORD_FIRST_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30875Byte 0 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RFOURTH_DWORD_SECOND_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30888Byte 1 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RFOURTH_DWORD_THIRD_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30901Byte 2 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RFOURTH_DWORD_FOURTH_BYTEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_GETDBI_SLAVE_PF0_AER_CAP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30914Byte 3 of Header log register of Fourth 32 bit Data Word.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_1_OFFTLP_PREFIX_LOG_1_OFFDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr309660x38R0x00000000DBI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFFTLP Prefix Log Register 1.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_1_FIRST_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30932Byte 0 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_1_SECOND_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30943Byte 1 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_1_THIRD_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30954Byte 2 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_1_FOURTH_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30965Byte 3 of Error TLP Prefix Log 1.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_2_OFFTLP_PREFIX_LOG_2_OFFDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr310170x3CR0x00000000DBI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFFTLP Prefix Log Register 2.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_2_FIRST_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30983Byte 0 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_2_SECOND_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr30994Byte 1 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_2_THIRD_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr31005Byte 2 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_2_FOURTH_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr31016Byte 3 Error TLP Prefix Log 2.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_3_OFFTLP_PREFIX_LOG_3_OFFDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr310680x40R0x00000000DBI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFFTLP Prefix Log Register 3.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_3_FIRST_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr31034Byte 0 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_3_SECOND_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr31045Byte 1 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_3_THIRD_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr31056Byte 2 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_3_FOURTH_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr31067Byte 3 Error TLP Prefix Log 3.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RregisterDBI_Slave.PF0_AER_CAP.TLP_PREFIX_LOG_4_OFFTLP_PREFIX_LOG_4_OFFDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_ADDRESSDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_OFFSETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr311190x44R0x00000000DBI_Slave_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFFTLP Prefix Log Register 4.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseCFG_TLP_PFX_LOG_4_FIRST_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr31085Byte 0 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.700x00RCFG_TLP_PFX_LOG_4_SECOND_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr31096Byte 1 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1580x00RCFG_TLP_PFX_LOG_4_THIRD_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr31107Byte 2 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.23160x00RCFG_TLP_PFX_LOG_4_FOURTH_BYTEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_WIDTHDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_LSBDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_RANGEDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_RESETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_FIELD_MASKDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_GETDBI_SLAVE_PF0_AER_CAP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SETDWC_pcie_wire_cpcie_usp_4x8.csr31118Byte 3 Error TLP Prefix Log 4.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.31240x00RgroupDBI_Slave.PF0_VC_CAPPF0_VC_CAPDBI_SLAVE_PF0_VC_CAP_ADDRESSDBI_SLAVE_PF0_VC_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_OFFSETDBI_SLAVE_PF0_VC_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr321120x148R/WDBI_Slave_PF0_VC_CAPVirtual Channel Capability StructureregisterDBI_Slave.PF0_VC_CAP.VC_BASEregisterDBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1registerDBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2registerDBI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGregisterDBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0registerDBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0registerDBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0registerDBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1registerDBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1registerDBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1registerDBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2registerDBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2registerDBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2registerDBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3registerDBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3registerDBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3registerDBI_Slave.PF0_VC_CAP.VC_BASEVC_BASEDBI_SLAVE_PF0_VC_CAP_VC_BASE_ADDRESSDBI_SLAVE_PF0_VC_CAP_VC_BASE_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_VC_BASE_OFFSETDBI_SLAVE_PF0_VC_CAP_VC_BASE_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr311790x0R0x19810002DBI_Slave_PF0_VC_CAP_VC_BASEVC Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PCIE_EXTENDED_CAP_IDDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_MSBDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_LSBDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_RANGEDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_RESETDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_GETDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr31146VC Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0002RVC_CAP_VERSIONDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_MSBDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_LSBDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_RANGEDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_RESETDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_GETDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr31162Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RVC_NEXT_OFFSETDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_MSBDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_LSBDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_RESETDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_GETDBI_SLAVE_PF0_VC_CAP_VC_BASE_VC_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr31178Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x198RregisterDBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_1VC_CAPABILITIES_REG_1DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_ADDRESSDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_OFFSETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr312490x4R0x00000003DBI_Slave_PF0_VC_CAP_VC_CAPABILITIES_REG_1Port VC Capability Register 1.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_EXT_VC_CNTDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_MSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_LSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_RANGEDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_RESETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_GETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr31194Extended VC Count.For a description of this standard PCIe register field, see the PCI Express Base Specification.200x3RRSVDP_3DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_MSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_LSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_RANGEDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_RESETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_GETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr31201Reserved for future use.330x0RVC_LOW_PRI_EXT_VC_CNTDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_MSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_LSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_RANGEDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_RESETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_GETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr31216Low Priority Extended VC Count.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.640x0RRSVDP_7DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_MSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_LSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_RANGEDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_RESETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_GETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr31223Reserved for future use.770x0RVC_REFERENCE_CLOCKDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_MSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_LSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_RANGEDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_RESETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_GETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_SETDWC_pcie_wire_cpcie_usp_4x8.csr31232Reference Clock.For a description of this standard PCIe register field, see the PCI Express Base Specification.980x0RVC_PORT_ARBI_TBL_ENTRY_SIZEDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_MSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_LSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_RANGEDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_RESETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_GETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr31241Port Arbitration Table Entry Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.11100x0RRSVDP_12DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_MSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_LSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_RANGEDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_RESETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_GETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_1_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr31248Reserved for future use.31120x00000RregisterDBI_Slave.PF0_VC_CAP.VC_CAPABILITIES_REG_2VC_CAPABILITIES_REG_2DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_ADDRESSDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_OFFSETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr312870x8R0x00000001DBI_Slave_PF0_VC_CAP_VC_CAPABILITIES_REG_2Port VC Capability Register 2.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_ARBI_CAPDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_MSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_LSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_RANGEDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_RESETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_GETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr31270VC Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.300x1RRSVDP_4DBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_MSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_LSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_RANGEDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_RESETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_GETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr31277Reserved for future use.2340x00000RVC_ARBI_TABLE_OFFSETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_MSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_LSBDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_RANGEDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_RESETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_GETDBI_SLAVE_PF0_VC_CAP_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr31286VC Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterDBI_Slave.PF0_VC_CAP.VC_STATUS_CONTROL_REGVC_STATUS_CONTROL_REGDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_ADDRESSDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_OFFSETDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr313380xCR/W0x00000000DBI_Slave_PF0_VC_CAP_VC_STATUS_CONTROL_REGPort VC Control and Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_LOAD_VC_ARBI_TABLEDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_MSBDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_LSBDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_RANGEDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_RESETDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_GETDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr31302Requests Hardware to Load VC Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_ARBI_SELECTDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_MSBDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_LSBDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_RANGEDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_RESETDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_GETDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr31311VC Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.310x0R/WRSVDP_4DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_MSBDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_LSBDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_RANGEDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_RESETDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_GETDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr31319Reserved for future use.1540x000RVC_ARBI_TABLE_STATUSDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_MSBDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_LSBDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_RANGEDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_RESETDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_GETDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr31329VC Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RRSVDP_17DBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_WIDTHDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_MSBDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_LSBDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_RANGEDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_RESETDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_GETDBI_SLAVE_PF0_VC_CAP_VC_STATUS_CONTROL_REG_RSVDP_17_SETDWC_pcie_wire_cpcie_usp_4x8.csr31337Reserved for future use.31170x0000RregisterDBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC0RESOURCE_CAP_REG_VC0DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_OFFSETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr314030x10R0x00000000DBI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC0VC Resource Capability Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC0DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr31353Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr31360Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC0DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr31373Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC0DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr31386Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr31393Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC0DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr31402Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterDBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC0RESOURCE_CON_REG_VC0DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_OFFSETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr314920x14R/W0x800000ffDBI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC0VC Resource Control Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC0DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr31418Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RVC_TC_MAP_VC0_BIT1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31427Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x7fR/WRSVDP_8DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr31435Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC0DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr31445Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC0DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr31455Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.17170x0RRSVDP_18DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr31463Reserved for future use.23180x00RVC_ID_VCDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ID_VC_SETDWC_pcie_wire_cpcie_usp_4x8.csr31473VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0RRSVDP_27DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr31481Reserved for future use.30270x0RVC_ENABLE_VC0DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr31491VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x1RregisterDBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC0RESOURCE_STATUS_REG_VC0DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_OFFSETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr315320x18R0x00000000DBI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0VC Resource Status Register (0).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr31505Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC0DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr31514Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC0DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr31524VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC0_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr31531Reserved for future use.31180x0000RregisterDBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC1RESOURCE_CAP_REG_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_OFFSETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr315970x1CR0x00000000DBI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC1VC Resource Capability Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_CAP_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31547VC1 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr31554Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_REJECT_SNOOP_TRANS_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31567VC1 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_MAX_TIME_SLOT_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31580VC1 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr31587Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC1_VC_PORT_ARBI_TABLE_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31596VC1 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterDBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC1RESOURCE_CON_REG_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_OFFSETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr316850x20R/W0x00000000DBI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC1VC Resource Control Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31612VC1 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC1_BIT1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_TC_MAP_VC1_BIT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31621VC1 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr31629Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_LOAD_PORT_ARBI_TABLE_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31639VC1 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_PORT_ARBI_SELECT_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31649VC1 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_20_SETDWC_pcie_wire_cpcie_usp_4x8.csr31657Reserved for future use.23200x0RVC_ID_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ID_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31667VC1 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr31675Reserved for future use.30270x0RVC_ENABLE_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC1_VC_ENABLE_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31684VC1 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterDBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC1RESOURCE_STATUS_REG_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_OFFSETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr317250x24R0x00000000DBI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1VC Resource Status Register (1).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr31698Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_PORT_ARBI_TABLE_STATUS_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31707VC1 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC1DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_VC_NEGO_PENDING_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31717VC1 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC1_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr31724Reserved for future use.31180x0000RregisterDBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC2RESOURCE_CAP_REG_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_OFFSETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr317900x28R0x00000000DBI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC2VC Resource Capability Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_CAP_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr31740VC2 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr31747Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_REJECT_SNOOP_TRANS_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr31760VC2 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_MAX_TIME_SLOT_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr31773VC2 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr31780Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC2_VC_PORT_ARBI_TABLE_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr31789VC2 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterDBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC2RESOURCE_CON_REG_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_OFFSETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr318780x2CR/W0x00000000DBI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC2VC Resource Control Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr31805VC2 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC2_BIT1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_TC_MAP_VC2_BIT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr31814VC2 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr31822Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_LOAD_PORT_ARBI_TABLE_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr31832VC2 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_PORT_ARBI_SELECT_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr31842VC2 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_20_SETDWC_pcie_wire_cpcie_usp_4x8.csr31850Reserved for future use.23200x0RVC_ID_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ID_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr31860VC2 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr31868Reserved for future use.30270x0RVC_ENABLE_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC2_VC_ENABLE_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr31877VC2 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterDBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC2RESOURCE_STATUS_REG_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_OFFSETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr319180x30R0x00000000DBI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2VC Resource Status Register (2).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr31891Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_PORT_ARBI_TABLE_STATUS_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr31900VC2 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC2DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_VC_NEGO_PENDING_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr31910VC2 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC2_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr31917Reserved for future use.31180x0000RregisterDBI_Slave.PF0_VC_CAP.RESOURCE_CAP_REG_VC3RESOURCE_CAP_REG_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_OFFSETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr319830x34R0x00000000DBI_Slave_PF0_VC_CAP_RESOURCE_CAP_REG_VC3VC Resource Capability Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_PORT_ARBI_CAP_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_CAP_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr31933VC3 Port Arbitration Capability.For a description of this standard PCIe register field, see the PCI Express Base Specification.700x00RRSVDP_8DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr31940Reserved for future use.1480x00RVC_REJECT_SNOOP_TRANS_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_REJECT_SNOOP_TRANS_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr31953VC3 Reject Snoop Transactions.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 15150x0RVC_MAX_TIME_SLOT_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_MAX_TIME_SLOT_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr31966VC3 Maximum Time Slots-1 supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R 21160x00RRSVDP_22DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr31973Reserved for future use.23220x0RVC_PORT_ARBI_TABLE_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CAP_REG_VC3_VC_PORT_ARBI_TABLE_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr31982VC3 Port Arbitration Table Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.31240x00RregisterDBI_Slave.PF0_VC_CAP.RESOURCE_CON_REG_VC3RESOURCE_CON_REG_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_OFFSETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr320710x38R/W0x00000000DBI_Slave_PF0_VC_CAP_RESOURCE_CON_REG_VC3VC Resource Control Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseVC_TC_MAP_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr31998VC3 Bit 0 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x0RVC_TC_MAP_VC3_BIT1DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_TC_MAP_VC3_BIT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr32007VC3 Bits 7:1 of TC to VC Mapping.For a description of this standard PCIe register field, see the PCI Express Base Specification.710x00R/WRSVDP_8DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr32015Reserved for future use.1580x00RVC_LOAD_PORT_ARBI_TABLE_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_LOAD_PORT_ARBI_TABLE_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr32025VC3 Load Port Arbitration Table.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0WVC_PORT_ARBI_SELECT_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_PORT_ARBI_SELECT_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr32035VC3 Port Arbitration Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.19170x0RRSVDP_20DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_20_SETDWC_pcie_wire_cpcie_usp_4x8.csr32043Reserved for future use.23200x0RVC_ID_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ID_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr32053VC3 VC ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.26240x0R/WRSVDP_27DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr32061Reserved for future use.30270x0RVC_ENABLE_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_CON_REG_VC3_VC_ENABLE_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr32070VC3 VC Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.31310x0R/WregisterDBI_Slave.PF0_VC_CAP.RESOURCE_STATUS_REG_VC3RESOURCE_STATUS_REG_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_BYTE_ADDRESSDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_OFFSETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr321110x3CR0x00000000DBI_Slave_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3VC Resource Status Register (3).For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr32084Reserved for future use.1500x0000RVC_PORT_ARBI_TABLE_STATUS_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_PORT_ARBI_TABLE_STATUS_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr32093VC3 Port Arbitration Table Status.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0RVC_NEGO_PENDING_VC3DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_VC_NEGO_PENDING_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr32103VC3 VC Negotiation Pending.For a description of this standard PCIe register field, see the PCI Express Base Specification.1717RRSVDP_18DBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_WIDTHDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_MSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_LSBDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_RANGEDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_RESETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_FIELD_MASKDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_GETDBI_SLAVE_PF0_VC_CAP_RESOURCE_STATUS_REG_VC3_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr32110Reserved for future use.31180x0000RgroupDBI_Slave.PF0_SPCIE_CAPPF0_SPCIE_CAPDBI_SLAVE_PF0_SPCIE_CAP_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_OFFSETDBI_SLAVE_PF0_SPCIE_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr328090x198R/WDBI_Slave_PF0_SPCIE_CAPSecondary PCI Express Capability StructureregisterDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGregisterDBI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGregisterDBI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGregisterDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGregisterDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGregisterDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGregisterDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGregisterDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_HEADER_REGSPCIE_CAP_HEADER_REGDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_BYTE_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_OFFSETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr321710x0R0x1b810019DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REGSPCIE Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseEXTENDED_CAP_IDDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr32138Secondary PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0019RCAP_VERSIONDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr32154Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr32170Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x1b8RregisterDBI_Slave.PF0_SPCIE_CAP.LINK_CONTROL3_REGLINK_CONTROL3_REGDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_BYTE_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_OFFSETDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr322120x4R0x00000000DBI_Slave_PF0_SPCIE_CAP_LINK_CONTROL3_REGLink Control 3 Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalsePERFORM_EQDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_MSBDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_LSBDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_RANGEDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_RESETDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_GETDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_PERFORM_EQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr32191Perform Equalization.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP 00REQ_REQ_INT_ENDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_MSBDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_LSBDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_RANGEDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_RESETDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_GETDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr32204Link Equalization Request Interrupt Enable.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: RSVDP 110x0RRSVDP_2DBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_MSBDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_LSBDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_RANGEDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_RESETDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_GETDBI_SLAVE_PF0_SPCIE_CAP_LINK_CONTROL3_REG_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr32211Reserved for future use.3120x00000000RregisterDBI_Slave.PF0_SPCIE_CAP.LANE_ERR_STATUS_REGLANE_ERR_STATUS_REGDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_BYTE_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_OFFSETDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr322370x8R/W0x00000000DBI_Slave_PF0_SPCIE_CAP_LANE_ERR_STATUS_REGLane Error Status Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseLANE_ERR_STATUSDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_MSBDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_LSBDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_RANGEDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_RESETDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_GETDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr32228Lane Error Status Bits per Lane.For a description of this standard PCIe register field, see the PCI Express Specification.700x00R/W1CRSVDP_LANE_ERR_STATUSDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_MSBDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_LSBDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_RANGEDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_RESETDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_GETDBI_SLAVE_PF0_SPCIE_CAP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr32236Reserved for future use.3180x000000RregisterDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_0CH_REGSPCIE_CAP_OFF_0CH_REGDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_BYTE_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_OFFSETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr323760xCR0x00000000DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REGLane Equalization Control Register for lanes 1 and 0.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET0DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_SETDWC_pcie_wire_cpcie_usp_4x8.csr32253Downstream Port 8.0 GT/s Transmitter Preset 0.For a description of this standard PCIe register field, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT0DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_SETDWC_pcie_wire_cpcie_usp_4x8.csr32263Downstream Port 8.0 GT/s Receiver Preset Hint 0.For a description of this standard PCIe register field, see the PCI Express Specification.640x0RRSVDP_7DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr32270Reserved for future use.770x0RUSP_TX_PRESET0DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_SETDWC_pcie_wire_cpcie_usp_4x8.csr32286Upstream Port 8.0 GT/s Transmitter Preset 0.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT0DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_SETDWC_pcie_wire_cpcie_usp_4x8.csr32302Upstream Port 8.0 GT/s Receiver Preset Hint 0.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr32309Reserved for future use.15150x0RDSP_TX_PRESET1DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_SETDWC_pcie_wire_cpcie_usp_4x8.csr32319Downstream Port 8.0 GT/s Transmitter Preset 1.For a description of this standard PCIe register field, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT1DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr32329Downstream Port 8.0 GT/s Receiver Preset Hint 1.For a description of this standard PCIe register field, see the PCI Express Specification.22200x0RRSVDP_23DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr32336Reserved for future use.23230x0RUSP_TX_PRESET1DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_SETDWC_pcie_wire_cpcie_usp_4x8.csr32352Upstream Port 8.0 GT/s Transmitter Preset 1.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT1DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr32368Upstream Port 8.0 GT/s Receiver Preset Hint 1.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_0CH_REG_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr32375Reserved for future use.31310x0RregisterDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_10H_REGSPCIE_CAP_OFF_10H_REGDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_BYTE_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_OFFSETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr325200x10R0x00000000DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #2.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET2DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_SETDWC_pcie_wire_cpcie_usp_4x8.csr32397Downstream Port 8.0 GT/s Transmitter Preset2.For a description of this standard PCIe register, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT2DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_SETDWC_pcie_wire_cpcie_usp_4x8.csr32407Downstream Port 8.0 GT/s Receiver Preset Hint2.For a description of this standard PCIe register, see the PCI Express Specification.640x0RRSVDP_7DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr32414Reserved for future use.770x0RUSP_TX_PRESET2DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_SETDWC_pcie_wire_cpcie_usp_4x8.csr32430Upstream Port 8.0 GT/s Transmitter Preset2.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT2DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_SETDWC_pcie_wire_cpcie_usp_4x8.csr32446Upstream Port 8.0 GT/s Receiver Preset Hint2.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr32453Reserved for future use.15150x0RDSP_TX_PRESET3DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_SETDWC_pcie_wire_cpcie_usp_4x8.csr32463Downstream Port 8.0 GT/s Transmitter Preset3.For a description of this standard PCIe register, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT3DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_SETDWC_pcie_wire_cpcie_usp_4x8.csr32473Downstream Port 8.0 GT/s Receiver Preset Hint3.For a description of this standard PCIe register, see the PCI Express Specification.22200x0RRSVDP_23DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr32480Reserved for future use.23230x0RUSP_TX_PRESET3DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_SETDWC_pcie_wire_cpcie_usp_4x8.csr32496Upstream Port 8.0 GT/s Transmitter Preset3.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT3DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_SETDWC_pcie_wire_cpcie_usp_4x8.csr32512Upstream Port 8.0 GT/s Receiver Preset Hint3.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_10H_REG_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr32519Reserved for future use.31310x0RregisterDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_14H_REGSPCIE_CAP_OFF_14H_REGDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_BYTE_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_OFFSETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr326640x14R0x00000000DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #4.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET4DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_SETDWC_pcie_wire_cpcie_usp_4x8.csr32541Downstream Port 8.0 GT/s Transmitter Preset4.For a description of this standard PCIe register, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT4DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_SETDWC_pcie_wire_cpcie_usp_4x8.csr32551Downstream Port 8.0 GT/s Receiver Preset Hint4.For a description of this standard PCIe register, see the PCI Express Specification.640x0RRSVDP_7DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr32558Reserved for future use.770x0RUSP_TX_PRESET4DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_SETDWC_pcie_wire_cpcie_usp_4x8.csr32574Upstream Port 8.0 GT/s Transmitter Preset4.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT4DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_SETDWC_pcie_wire_cpcie_usp_4x8.csr32590Upstream Port 8.0 GT/s Receiver Preset Hint4.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr32597Reserved for future use.15150x0RDSP_TX_PRESET5DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_SETDWC_pcie_wire_cpcie_usp_4x8.csr32607Downstream Port 8.0 GT/s Transmitter Preset5.For a description of this standard PCIe register, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT5DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_SETDWC_pcie_wire_cpcie_usp_4x8.csr32617Downstream Port 8.0 GT/s Receiver Preset Hint5.For a description of this standard PCIe register, see the PCI Express Specification.22200x0RRSVDP_23DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr32624Reserved for future use.23230x0RUSP_TX_PRESET5DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_SETDWC_pcie_wire_cpcie_usp_4x8.csr32640Upstream Port 8.0 GT/s Transmitter Preset5.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT5DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_SETDWC_pcie_wire_cpcie_usp_4x8.csr32656Upstream Port 8.0 GT/s Receiver Preset Hint5.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_14H_REG_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr32663Reserved for future use.31310x0RregisterDBI_Slave.PF0_SPCIE_CAP.SPCIE_CAP_OFF_18H_REGSPCIE_CAP_OFF_18H_REGDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_BYTE_ADDRESSDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_OFFSETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr328080x18R0x00000000DBI_Slave_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REGLane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #6.The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseDSP_TX_PRESET6DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_SETDWC_pcie_wire_cpcie_usp_4x8.csr32685Downstream Port 8.0 GT/s Transmitter Preset6.For a description of this standard PCIe register, see the PCI Express Specification.300x0RDSP_RX_PRESET_HINT6DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_SETDWC_pcie_wire_cpcie_usp_4x8.csr32695Downstream Port 8.0 GT/s Receiver Preset Hint6.For a description of this standard PCIe register, see the PCI Express Specification.640x0RRSVDP_7DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr32702Reserved for future use.770x0RUSP_TX_PRESET6DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_SETDWC_pcie_wire_cpcie_usp_4x8.csr32718Upstream Port 8.0 GT/s Transmitter Preset6.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.118RUSP_RX_PRESET_HINT6DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_SETDWC_pcie_wire_cpcie_usp_4x8.csr32734Upstream Port 8.0 GT/s Receiver Preset Hint6.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1412RRSVDP_15DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr32741Reserved for future use.15150x0RDSP_TX_PRESET7DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_SETDWC_pcie_wire_cpcie_usp_4x8.csr32751Downstream Port 8.0 GT/s Transmitter Preset7.For a description of this standard PCIe register, see the PCI Express Specification.19160x0RDSP_RX_PRESET_HINT7DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_SETDWC_pcie_wire_cpcie_usp_4x8.csr32761Downstream Port 8.0 GT/s Receiver Preset Hint7.For a description of this standard PCIe register, see the PCI Express Specification.22200x0RRSVDP_23DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr32768Reserved for future use.23230x0RUSP_TX_PRESET7DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_SETDWC_pcie_wire_cpcie_usp_4x8.csr32784Upstream Port 8.0 GT/s Transmitter Preset7.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.2724RUSP_RX_PRESET_HINT7DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_SETDWC_pcie_wire_cpcie_usp_4x8.csr32800Upstream Port 8.0 GT/s Receiver Preset Hint7.The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.3028RRSVDP_31DBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_WIDTHDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_MSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_LSBDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_RANGEDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_RESETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_FIELD_MASKDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_GETDBI_SLAVE_PF0_SPCIE_CAP_SPCIE_CAP_OFF_18H_REG_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr32807Reserved for future use.31310x0RgroupDBI_Slave.PF0_PL16G_CAPPF0_PL16G_CAPDBI_SLAVE_PF0_PL16G_CAP_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_OFFSETDBI_SLAVE_PF0_PL16G_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr332280x1B8R/WDBI_Slave_PF0_PL16G_CAPPhysical Layer 16.0 GT/s Extended Capability StructureregisterDBI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGregisterDBI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGregisterDBI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGregisterDBI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGregisterDBI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGregisterDBI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGregisterDBI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGregisterDBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGregisterDBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGregisterDBI_Slave.PF0_PL16G_CAP.PL16G_EXT_CAP_HDR_REGPL16G_EXT_CAP_HDR_REGDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_OFFSETDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr328680x0R0x1e010026DBI_Slave_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REGPhysical Layer 16.0 GT/s Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEXTENDED_CAP_IDDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr32835PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0026RCAP_VERSIONDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr32851Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_EXT_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr32867Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x1e0RregisterDBI_Slave.PF0_PL16G_CAP.PL16G_CAPABILITY_REGPL16G_CAPABILITY_REGDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_OFFSETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr328820x4R0x00000000DBI_Slave_PF0_PL16G_CAP_PL16G_CAPABILITY_REG16.0 GT/s Capabilities Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAPABILITY_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr32881Reserved for future use.3100x00000000RregisterDBI_Slave.PF0_PL16G_CAP.PL16G_CONTROL_REGPL16G_CONTROL_REGDBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_OFFSETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr328960x8R0x00000000DBI_Slave_PF0_PL16G_CAP_PL16G_CONTROL_REG16.0 GT/s Control Register .For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CONTROL_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr32895Reserved for future use.3100x00000000RregisterDBI_Slave.PF0_PL16G_CAP.PL16G_STATUS_REGPL16G_STATUS_REGDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_OFFSETDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr329770xCR/W0x00000000DBI_Slave_PF0_PL16G_CAP_PL16G_STATUS_REG16.0 GT/s Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEQ_16G_CPLDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_SETDWC_pcie_wire_cpcie_usp_4x8.csr32915Equalization 16.0GT/s Complete.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.000x0REQ_16G_CPL_P1DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P1_SETDWC_pcie_wire_cpcie_usp_4x8.csr32929Equalization 16.0GT/s Phase 1 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.110x0REQ_16G_CPL_P2DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P2_SETDWC_pcie_wire_cpcie_usp_4x8.csr32943Equalization 16.0GT/s Phase 2 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.220x0REQ_16G_CPL_P3DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_EQ_16G_CPL_P3_SETDWC_pcie_wire_cpcie_usp_4x8.csr32957Equalization 16.0GT/s Phase 3 Successful.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: This register field is sticky.330x0RLINK_EQ_16G_REQDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_LINK_EQ_16G_REQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr32968Link Equalization Request 16.0GT/s.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.440x0R/W1CRSVDP_5DBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_STATUS_REG_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr32976Reserved for future use.3150x0000000RregisterDBI_Slave.PF0_PL16G_CAP.PL16G_LC_DPAR_STATUS_REGPL16G_LC_DPAR_STATUS_REGDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_OFFSETDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr330020x10R/W0x00000000DBI_Slave_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG16.0 GT/s Local Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseLC_DPAR_STATUSDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_LC_DPAR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr32993Local Data Parity Mismatch Status.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_LC_DPAR_STATUSDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_LC_DPAR_STATUS_REG_RSVDP_LC_DPAR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33001Reserved for future use.3180x000000RregisterDBI_Slave.PF0_PL16G_CAP.PL16G_FIRST_RETIMER_DPAR_STATUS_REGPL16G_FIRST_RETIMER_DPAR_STATUS_REGDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_OFFSETDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr330270x14R/W0x00000000DBI_Slave_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG16.0 GT/s First Retimer Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseFIRST_RETIMER_DPAR_STATUSDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_FIRST_RETIMER_DPAR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33018First Retimer Data Parity Mismatch Status.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_FIRST_RETIMER_DPAR_STATUSDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_FIRST_RETIMER_DPAR_STATUS_REG_RSVDP_FIRST_RETIMER_DPAR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33026Reserved for future use.3180x000000RregisterDBI_Slave.PF0_PL16G_CAP.PL16G_SECOND_RETIMER_DPAR_STATUS_REGPL16G_SECOND_RETIMER_DPAR_STATUS_REGDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_OFFSETDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr330530x18R/W0x00000000DBI_Slave_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG16.0 GT/s Second Retimer Data Parity Mismatch Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseSECOND_RETIMER_DPAR_STATUSDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_SECOND_RETIMER_DPAR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33044Second Retimer Data Parity Mismatch Status .For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.700x00R/W1CRSVDP_SECOND_RETIMER_DPAR_STATUSDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_SECOND_RETIMER_DPAR_STATUS_REG_RSVDP_SECOND_RETIMER_DPAR_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33052Reserved for future use.3180x000000RregisterDBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_20H_REGPL16G_CAP_OFF_20H_REGDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_OFFSETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr331400x20R0x00000000DBI_Slave_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG16.0 GT/s Lane Equalization Control Register for Lane 0-3.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseDSP_16G_TX_PRESET0DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET0_SETDWC_pcie_wire_cpcie_usp_4x8.csr33069Downstream Port 16.0 GT/s Transmitter Preset0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.300x0RUSP_16G_TX_PRESET0DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET0_SETDWC_pcie_wire_cpcie_usp_4x8.csr33079Upstream Port 16.0 GT/s Transmitter Preset0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.740x0RDSP_16G_TX_PRESET1DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET1_SETDWC_pcie_wire_cpcie_usp_4x8.csr33089Downstream Port 16.0 GT/s Transmitter Preset1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1180x0RUSP_16G_TX_PRESET1DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET1_SETDWC_pcie_wire_cpcie_usp_4x8.csr33099Upstream Port 16.0 GT/s Transmitter Preset1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.15120x0RDSP_16G_TX_PRESET2DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET2_SETDWC_pcie_wire_cpcie_usp_4x8.csr33109Downstream Port 16.0 GT/s Transmitter Preset2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.19160x0RUSP_16G_TX_PRESET2DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET2_SETDWC_pcie_wire_cpcie_usp_4x8.csr33119Upstream Port 16.0 GT/s Transmitter Preset2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.23200x0RDSP_16G_TX_PRESET3DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_DSP_16G_TX_PRESET3_SETDWC_pcie_wire_cpcie_usp_4x8.csr33129Downstream Port 16.0 GT/s Transmitter Preset3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.27240x0RUSP_16G_TX_PRESET3DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_20H_REG_USP_16G_TX_PRESET3_SETDWC_pcie_wire_cpcie_usp_4x8.csr33139Upstream Port 16.0 GT/s Transmitter Preset3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31280x0RregisterDBI_Slave.PF0_PL16G_CAP.PL16G_CAP_OFF_24H_REGPL16G_CAP_OFF_24H_REGDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_BYTE_ADDRESSDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_OFFSETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr332270x24R0x00000000DBI_Slave_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG16.0 GT/s Lane Equalization Control Register for Lane 4-7.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseDSP_16G_TX_PRESET4DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET4_SETDWC_pcie_wire_cpcie_usp_4x8.csr33156Downstream Port 16.0 GT/s Transmitter Preset4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.300x0RUSP_16G_TX_PRESET4DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET4_SETDWC_pcie_wire_cpcie_usp_4x8.csr33166Upstream Port 16.0 GT/s Transmitter Preset4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.740x0RDSP_16G_TX_PRESET5DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET5_SETDWC_pcie_wire_cpcie_usp_4x8.csr33176Downstream Port 16.0 GT/s Transmitter Preset5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1180x0RUSP_16G_TX_PRESET5DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET5_SETDWC_pcie_wire_cpcie_usp_4x8.csr33186Upstream Port 16.0 GT/s Transmitter Preset5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.15120x0RDSP_16G_TX_PRESET6DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET6_SETDWC_pcie_wire_cpcie_usp_4x8.csr33196Downstream Port 16.0 GT/s Transmitter Preset6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.19160x0RUSP_16G_TX_PRESET6DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET6_SETDWC_pcie_wire_cpcie_usp_4x8.csr33206Upstream Port 16.0 GT/s Transmitter Preset6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.23200x0RDSP_16G_TX_PRESET7DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_DSP_16G_TX_PRESET7_SETDWC_pcie_wire_cpcie_usp_4x8.csr33216Downstream Port 16.0 GT/s Transmitter Preset7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.27240x0RUSP_16G_TX_PRESET7DBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_WIDTHDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_MSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_LSBDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_RANGEDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_RESETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_FIELD_MASKDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_GETDBI_SLAVE_PF0_PL16G_CAP_PL16G_CAP_OFF_24H_REG_USP_16G_TX_PRESET7_SETDWC_pcie_wire_cpcie_usp_4x8.csr33226Upstream Port 16.0 GT/s Transmitter Preset7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31280x0RgroupDBI_Slave.PF0_MARGIN_CAPPF0_MARGIN_CAPDBI_SLAVE_PF0_MARGIN_CAP_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_OFFSETDBI_SLAVE_PF0_MARGIN_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr342170x1E0R/WDBI_Slave_PF0_MARGIN_CAPMargining Extended Capability StructureregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_EXT_CAP_HDR_REGMARGIN_EXT_CAP_HDR_REGDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_OFFSETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr332870x0R0x20810027DBI_Slave_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REGMargining Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseEXTENDED_CAP_IDDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_EXTENDED_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr33254PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0027RCAP_VERSIONDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr33270Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_EXT_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr33286Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x208RregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_PORT_CAPABILITIES_STATUS_REGMARGIN_PORT_CAPABILITIES_STATUS_REGDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_OFFSETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr333440x4R0x00000000DBI_Slave_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REGMargining Port Capabilities and Status Register.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseMARGINING_USES_DRIVER_SOFTWAREDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_USES_DRIVER_SOFTWARE_SETDWC_pcie_wire_cpcie_usp_4x8.csr33309Margining uses Driver Software.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.000x0RRSVDP_1DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr33316Reserved for future use.1510x0000RMARGINING_READYDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_READY_SETDWC_pcie_wire_cpcie_usp_4x8.csr33326Margining Ready.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.1616RMARGINING_SOFTWARE_READYDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_MARGINING_SOFTWARE_READY_SETDWC_pcie_wire_cpcie_usp_4x8.csr33336Margining Software Ready.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.1717RRSVDP_18DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_PORT_CAPABILITIES_STATUS_REG_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr33343Reserved for future use.31180x0000RregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS0_REGMARGIN_LANE_CNTRL_STATUS0_REGDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_OFFSETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr334530x8R/W0x00009c38DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REGMargining Lane Control and Status Register for Lane 0.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr33358Receiver Number for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr33368Margin Type for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr33378Usage Model for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr33386Reserved for future use.770x0RMARGIN_PAYLOADDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr33396Margin Payload for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33408Receiver Number(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33420Margin Type(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33432Usage Model(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr33440Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS0_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33452Margin Payload(Status) for Lane 0.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS1_REGMARGIN_LANE_CNTRL_STATUS1_REGDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_OFFSETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr335620xCR/W0x00009c38DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REGMargining Lane Control and Status Register for Lane 1.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr33467Receiver Number for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr33477Margin Type for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr33487Usage Model for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr33495Reserved for future use.770x0RMARGIN_PAYLOADDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr33505Margin Payload for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33517Receiver Number(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33529Margin Type(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33541Usage Model(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr33549Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS1_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33561Margin Payload(Status) for Lane 1.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS2_REGMARGIN_LANE_CNTRL_STATUS2_REGDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_OFFSETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr336710x10R/W0x00009c38DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REGMargining Lane Control and Status Register for Lane 2.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr33576Receiver Number for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr33586Margin Type for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr33596Usage Model for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr33604Reserved for future use.770x0RMARGIN_PAYLOADDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr33614Margin Payload for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33626Receiver Number(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33638Margin Type(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33650Usage Model(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr33658Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS2_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33670Margin Payload(Status) for Lane 2.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS3_REGMARGIN_LANE_CNTRL_STATUS3_REGDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_OFFSETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr337800x14R/W0x00009c38DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REGMargining Lane Control and Status Register for Lane 3.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr33685Receiver Number for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr33695Margin Type for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr33705Usage Model for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr33713Reserved for future use.770x0RMARGIN_PAYLOADDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr33723Margin Payload for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33735Receiver Number(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33747Margin Type(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33759Usage Model(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr33767Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS3_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33779Margin Payload(Status) for Lane 3.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS4_REGMARGIN_LANE_CNTRL_STATUS4_REGDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_OFFSETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr338890x18R/W0x00009c38DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REGMargining Lane Control and Status Register for Lane 4.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr33794Receiver Number for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr33804Margin Type for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr33814Usage Model for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr33822Reserved for future use.770x0RMARGIN_PAYLOADDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr33832Margin Payload for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33844Receiver Number(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33856Margin Type(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33868Usage Model(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr33876Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS4_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33888Margin Payload(Status) for Lane 4.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS5_REGMARGIN_LANE_CNTRL_STATUS5_REGDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_OFFSETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr339980x1CR/W0x00009c38DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REGMargining Lane Control and Status Register for Lane 5.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr33903Receiver Number for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr33913Margin Type for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr33923Usage Model for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr33931Reserved for future use.770x0RMARGIN_PAYLOADDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr33941Margin Payload for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33953Receiver Number(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33965Margin Type(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33977Usage Model(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr33985Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS5_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr33997Margin Payload(Status) for Lane 5.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS6_REGMARGIN_LANE_CNTRL_STATUS6_REGDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_OFFSETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr341070x20R/W0x00009c38DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REGMargining Lane Control and Status Register for Lane 6.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr34012Receiver Number for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr34022Margin Type for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr34032Usage Model for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr34040Reserved for future use.770x0RMARGIN_PAYLOADDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr34050Margin Payload for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr34062Receiver Number(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr34074Margin Type(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr34086Usage Model(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr34094Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS6_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr34106Margin Payload(Status) for Lane 6.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RregisterDBI_Slave.PF0_MARGIN_CAP.MARGIN_LANE_CNTRL_STATUS7_REGMARGIN_LANE_CNTRL_STATUS7_REGDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_BYTE_ADDRESSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_OFFSETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr342160x24R/W0x00009c38DBI_Slave_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REGMargining Lane Control and Status Register for Lane 7.For a description of this standard PCIe register, see the PCI Express Base Specification 4.0.falsefalsefalsefalseRECEIVER_NUMBERDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr34121Receiver Number for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.200x0R/WMARGIN_TYPEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr34131Margin Type for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.530x7R/WUSAGE_MODELDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr34141Usage Model for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.660x0R/WRSVDP_7DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr34149Reserved for future use.770x0RMARGIN_PAYLOADDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_SETDWC_pcie_wire_cpcie_usp_4x8.csr34159Margin Payload for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.1580x9cR/WRECEIVER_NUMBER_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RECEIVER_NUMBER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr34171Receiver Number(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.18160x0RMARGIN_TYPE_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_TYPE_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr34183Margin Type(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.21190x0RUSAGE_MODEL_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_USAGE_MODEL_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr34195Usage Model(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.22220x0RRSVDP_23DBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr34203Reserved for future use.23230x0RMARGIN_PAYLOAD_STATUSDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_WIDTHDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_MSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_LSBDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_RANGEDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_RESETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_FIELD_MASKDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_GETDBI_SLAVE_PF0_MARGIN_CAP_MARGIN_LANE_CNTRL_STATUS7_REG_MARGIN_PAYLOAD_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr34215Margin Payload(Status) for Lane 7.For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.31240x00RgroupDBI_Slave.PF0_TPH_CAPPF0_TPH_CAPDBI_SLAVE_PF0_TPH_CAP_ADDRESSDBI_SLAVE_PF0_TPH_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_TPH_CAP_OFFSETDBI_SLAVE_PF0_TPH_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr345000x208R/WDBI_Slave_PF0_TPH_CAPPF TLP Processing Hints Capability StructureregisterDBI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGregisterDBI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGregisterDBI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGregisterDBI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0registerDBI_Slave.PF0_TPH_CAP.TPH_EXT_CAP_HDR_REGTPH_EXT_CAP_HDR_REGDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_ADDRESSDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_OFFSETDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr342760x0R0x29410017DBI_Slave_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REGTPH Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalsePCIE_EXT_CAP_IDDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_GETDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr34243TPH Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0017RTPH_REQ_CAP_VERDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_GETDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_SETDWC_pcie_wire_cpcie_usp_4x8.csr34259Capability Version.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RTPH_REQ_NEXT_PTRDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_GETDBI_SLAVE_PF0_TPH_CAP_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_SETDWC_pcie_wire_cpcie_usp_4x8.csr34275Next Capability Pointer.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x294RregisterDBI_Slave.PF0_TPH_CAP.TPH_REQ_CAP_REG_REGTPH_REQ_CAP_REG_REGDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_ADDRESSDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_OFFSETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr344150x4R0x00000001DBI_Slave_PF0_TPH_CAP_TPH_REQ_CAP_REG_REGTPH Requestor Capability Register.For a description of this standard PCIe register, see the PCI Express Base Specification.SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform aDBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register.falsefalsefalsefalseTPH_REQ_NO_ST_MODEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr34298No ST Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.000x1RTPH_REQ_CAP_INT_VECDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_SETDWC_pcie_wire_cpcie_usp_4x8.csr34314Interrupt Vector Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.110x0RTPH_REQ_DEVICE_SPECDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_SETDWC_pcie_wire_cpcie_usp_4x8.csr34330Device Specific Mode Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.220x0RRSVDP_3DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr34337Reserved for future use.730x00RTPH_REQ_EXTENDED_TPHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_SETDWC_pcie_wire_cpcie_usp_4x8.csr34353Extended TPH Requester Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RTPH_REQ_CAP_ST_TABLE_LOC_0DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr34369ST Table Location Bit 0.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RTPH_REQ_CAP_ST_TABLE_LOC_1DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr34385ST Table Location Bit 1.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RRSVDP_11DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_11_SETDWC_pcie_wire_cpcie_usp_4x8.csr34392Reserved for future use.15110x00RTPH_REQ_CAP_ST_TABLE_SIZEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr34407ST Table Size.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.26160x000RRSVDP_27DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CAP_REG_REG_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr34414Reserved for future use.31270x00RregisterDBI_Slave.PF0_TPH_CAP.TPH_REQ_CONTROL_REG_REGTPH_REQ_CONTROL_REG_REGDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_ADDRESSDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_BYTE_ADDRESSDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_OFFSETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr344600x8R/W0x00000000DBI_Slave_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REGTPH Requestor Control Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseTPH_REQ_ST_MODE_SELECTDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr34434ST Mode Select.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 200x0RRSVDP_3DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr34442Reserved for future use.730x00RTPH_REQ_CTRL_REQ_ENDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr34451TPH Requester Enable Bit.For a description of this standard PCIe register field, see the PCI Express Base Specification.980x0R/WRSVDP_10DBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_GETDBI_SLAVE_PF0_TPH_CAP_TPH_REQ_CONTROL_REG_REG_RSVDP_10_SETDWC_pcie_wire_cpcie_usp_4x8.csr34459Reserved for future use.31100x000000RregisterDBI_Slave.PF0_TPH_CAP.TPH_ST_TABLE_REG_0TPH_ST_TABLE_REG_0DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_ADDRESSDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_BYTE_ADDRESSDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_OFFSETDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr344990xCR/W0x00000000DBI_Slave_PF0_TPH_CAP_TPH_ST_TABLE_REG_0TPH ST Table Register 0.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseTPH_REQ_ST_TABLE_LOWER_0DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_GETDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr34481ST Table 0 Lower Byte.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: this field is RW or Tie to 0 by table size configure - Dbi: this field is RW or Tie to 0 by table size configure 700x00R/WTPH_REQ_ST_TABLE_HIGHER_0DBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_WIDTHDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_MSBDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_LSBDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_RANGEDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_RESETDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_FIELD_MASKDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_GETDBI_SLAVE_PF0_TPH_CAP_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr34498ST Table 0 Upper Byte.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: this field is RW or Tie to 0 by table size configure - Dbi: this field is RW or Tie to 0 by table size configure 1580x00R--31160x0rgroupDBI_Slave.PF0_LTR_CAPPF0_LTR_CAPDBI_SLAVE_PF0_LTR_CAP_ADDRESSDBI_SLAVE_PF0_LTR_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_LTR_CAP_OFFSETDBI_SLAVE_PF0_LTR_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr346520x294R/WDBI_Slave_PF0_LTR_CAPPF Latency Tolerance Reporting Capability StructureregisterDBI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REGregisterDBI_Slave.PF0_LTR_CAP.LTR_LATENCY_REGregisterDBI_Slave.PF0_LTR_CAP.LTR_CAP_HDR_REGLTR_CAP_HDR_REGDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_ADDRESSDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_BYTE_ADDRESSDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_OFFSETDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr34566This register provides capbility ID, capability version and next offset value for LTR(Latency Tolerance Reporting).0x0R0x29c10018DBI_Slave_PF0_LTR_CAP_LTR_CAP_HDR_REGLTR Extended Capability Header.This register provides capbility ID, capability version and next offset value for LTR(Latency Tolerance Reporting).falsefalsefalsefalseCAP_IDDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_WIDTHDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_MSBDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_LSBDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_RANGEDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_RESETDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_GETDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr34531LTR Extended Capacity ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.PCI Express Extended Capability for the LTR Extended Capability is 0018h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0018RCAP_VERSIONDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_WIDTHDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_MSBDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_LSBDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_RANGEDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_RESETDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_FIELD_MASKDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_GETDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr34548Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_MSBDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_LSBDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_RESETDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_GETDBI_SLAVE_PF0_LTR_CAP_LTR_CAP_HDR_REG_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr34565Next Capability Offset.This field contains the offset to the next PCI Express Extended Capability structure or 000h if no other items exist in the linked list of Capabilities.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x29cRregisterDBI_Slave.PF0_LTR_CAP.LTR_LATENCY_REGLTR_LATENCY_REGDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_ADDRESSDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_BYTE_ADDRESSDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_OFFSETDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr34651This register indicates Latency scale and vlaue for Max Snoop and No-Snoop.0x4R/W0x00000000DBI_Slave_PF0_LTR_CAP_LTR_LATENCY_REGLTR Max Snoop and No-Snoop Latency Register.This register indicates Latency scale and vlaue for Max Snoop and No-Snoop.falsefalsefalsefalseMAX_SNOOP_LATDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_WIDTHDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_MSBDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_LSBDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_RANGEDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_RESETDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_FIELD_MASKDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_GETDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SETDWC_pcie_wire_cpcie_usp_4x8.csr34589Max Snoop Latency Value.Along with the Max Snoop LatencyScale field,this register specifies the maximum snoop latency that a device is permitted to request. Software should set this to the platform’s maximum supported latency or less.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 00 0000 0000b.900x000R/WMAX_SNOOP_LAT_SCALEDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_WIDTHDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_MSBDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_LSBDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_RANGEDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_RESETDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_FIELD_MASKDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_GETDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr34604Max Snoop Latency Scale.This register provides a scale for the value contained within the Max Snoop LatencyValue field. Encoding is the same as the LatencyScale fields in the LTR Message.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 000b.Hardware operation is undefined if software writes a Not Permitted value to this field.12100x0R/WRSVDP_13DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_WIDTHDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_MSBDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_LSBDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_RANGEDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_RESETDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_FIELD_MASKDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_GETDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_13_SETDWC_pcie_wire_cpcie_usp_4x8.csr34612Reserved for future use.15130x0RMAX_NO_SNOOP_LATDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_WIDTHDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_MSBDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_LSBDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_RANGEDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_RESETDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_FIELD_MASKDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_GETDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SETDWC_pcie_wire_cpcie_usp_4x8.csr34627Max No-Snoop Latency Value.Along with the Max No-Snoop LatencyScale field, this register specifies the maximum no-snoop latency that a device is permitted to request. Software should set this to the platform’s maximum supported latency or less.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 00 0000 0000b.25160x000R/WMAX_NO_SNOOP_LAT_SCALEDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_WIDTHDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_MSBDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_LSBDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_RANGEDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_RESETDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_FIELD_MASKDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_GETDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr34642Max No-Snoop Latency Scale.This register provides a scale for the value contained within the Max No-Snoop LatencyValue field. Encoding is the same as the LatencyScale fields in the LTR Message.It is strongly recommended that any updates to this field are reflected in LTR Message(s) sent by the device within 1 ms.The default value for this field is 000b.Hardware operation is undefined if software writes a Not Permitted value to this field.28260x0R/WRSVDP_29DBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_WIDTHDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_MSBDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_LSBDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_RANGEDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_RESETDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_FIELD_MASKDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_GETDBI_SLAVE_PF0_LTR_CAP_LTR_LATENCY_REG_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr34650Reserved for future use.31290x0RgroupDBI_Slave.PF0_L1SUB_CAPPF0_L1SUB_CAPDBI_SLAVE_PF0_L1SUB_CAP_ADDRESSDBI_SLAVE_PF0_L1SUB_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_L1SUB_CAP_OFFSETDBI_SLAVE_PF0_L1SUB_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr350970x29CR/WDBI_Slave_PF0_L1SUB_CAPL1 Substates Capability StructureregisterDBI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGregisterDBI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGregisterDBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGregisterDBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGregisterDBI_Slave.PF0_L1SUB_CAP.L1SUB_CAP_HEADER_REGL1SUB_CAP_HEADER_REGDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_ADDRESSDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_BYTE_ADDRESSDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_OFFSETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr34726L1 Substates Extended Capability Header provides capbility ID, capability version and next offset value for L1 Substates.0x0R0x2bc1001eDBI_Slave_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REGL1 Substates Extended Capability Header.This register provides capbility ID, capability version and next offset value for L1 Substates.falsefalsefalsefalseEXTENDED_CAP_IDDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr34683L1SUB Extended Capability ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.Extended Capability ID for L1 PM Substates is 001Eh.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x001eRCAP_VERSIONDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr34700Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr34725Next Capability Offset.This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities.For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x2bcRregisterDBI_Slave.PF0_L1SUB_CAP.L1SUB_CAPABILITY_REGL1SUB_CAPABILITY_REGDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_ADDRESSDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_BYTE_ADDRESSDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_OFFSETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr34889This register provides extended capability of L1 Substates.0x4R0x00380a1fDBI_Slave_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REGL1 Substates Capability Register.This register provides extended capability of L1 Substates.falsefalsefalsefalseL1_2_PCIPM_SUPPORTDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr34745PCI-PM L12 Supported.When Set this bit indicates that PCI-PM L1.2 is supported.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 000x1RL1_1_PCIPM_SUPPORTDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr34758PCI-PM L11 Supported.When Set this bit indicates that PCI-PM L1.1 is supported, and must be Set by all Ports implementing L1 PM Substates.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 110x1RL1_2_ASPM_SUPPORTDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr34770ASPM L12 Supported.When Set this bit indicates that ASPM L1.2 is supported.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 220x1RL1_1_ASPM_SUPPORTDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr34782ASPM L11 Supported.When Set this bit indicates that ASPM L1.1 is supported.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 330x1RL1_PMSUB_SUPPORTDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr34795L1 PM Substates ECN Supported.When Set this bit indicates that this Port supports L1 PM Substates.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: R/W (sticky) 440x1RRSVDP_5DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr34802Reserved for future use.750x0RCOMM_MODE_SUPPORTDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr34821Port Common Mode Restore Time.Time (in us) required for this Port to re-establish common mode.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 1580x0aRPWR_ON_SCALE_SUPPORTDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr34848Port T Power On Scale.Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register.Range of values are given below.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 17160x0RfalsetruefalseReserved0x3Reserved.RSVDP_18DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr34855Reserved for future use.18180x0RPWR_ON_VALUE_SUPPORTDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr34881Port T Power On Value.Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.The value of Port T_POWER_ON is calculated by multiplying the value in this field by the scale value in the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register. Default value is 00101b.Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set, ASPM L1.2 Supported bit is Set, or both are Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 23190x07RRSVDP_24DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CAPABILITY_REG_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr34888Reserved for future use.31240x00RregisterDBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL1_REGL1SUB_CONTROL1_REGDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_ADDRESSDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_BYTE_ADDRESSDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_OFFSETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr35012This register provides Controls to extended capability.0x8R/W0x00000000DBI_Slave_PF0_L1SUB_CAP_L1SUB_CONTROL1_REGL1 Substates Control 1 Register.This register provides Controls to extended capability.falsefalsefalsefalseL1_2_PCIPM_ENDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr34905PCI-PM L12 Enable.When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.000x0R/WL1_1_PCIPM_ENDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr34914PCI-PM L11 Enable.When Set this bit enables PCI-PM L1.1. Default value is 0b.110x0R/WL1_2_ASPM_ENDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr34924ASPM L12 Enable.When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.220x0R/WL1_1_ASPM_ENDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr34934ASPM L11 Enable.When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b.330x0R/WRSVDP_4DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr34942Reserved for future use.740x0RT_COMMON_MODEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_T_COMMON_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr34962Common Mode Restore Time.Sets value of TCOMMONMODE (in μs), which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports.Default value is implementation specific.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RW : RSVDP 1580x00RL1_2_TH_VALDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SETDWC_pcie_wire_cpcie_usp_4x8.csr34982LTR L12 Threshold Value.Along with the LTR_L1.2_THRESHOLD_Scale, this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b.Required for all Ports for which the ASPM L12 Supported bit is Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP 25160x000R/WRSVDP_26DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_RSVDP_26_SETDWC_pcie_wire_cpcie_usp_4x8.csr34990Reserved for future use.28260x0RL1_2_TH_SCADBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SETDWC_pcie_wire_cpcie_usp_4x8.csr35011LTR L12 Threshold Scale.This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field.Required for all Ports Ports for which the ASPM L12 Supported bit is Set, otherwise this field is of type RsvdP.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT ? RW : RSVDP 31290x0R/WregisterDBI_Slave.PF0_L1SUB_CAP.L1SUB_CONTROL2_REGL1SUB_CONTROL2_REGDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_ADDRESSDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_OFFSETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr35096This register provides Controls to extended capability.0xCR/W0x00000028DBI_Slave_PF0_L1SUB_CAP_L1SUB_CONTROL2_REGL1 Substates Control 2 Register.This register provides Controls to extended capability.falsefalsefalsefalseT_POWER_ON_SCALEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr35050T Power On Scale.Specifies the scale used for T_POWER_ON Value.Range of values are given below.Required for all Ports that support L1.2, otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear.The Port behavior is undefined if this field is modified when either the ASPM L1.2 Enable and/or PCI-PM L1.2 Enable bit(s) are Set.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 100x0R/WfalsetruefalseReserved0x3Reserved.RSVDP_2DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr35058Reserved for future use.220x0RT_POWER_ON_VALUEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr35087T Power On Value.Along with the T_POWER_ON Scale sets the minimum amount of time (in μs) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b.T_POWER_ON is calculated by multiplying the value in this field by the value in the T_POWER_ON Scale field.Required for all Ports that support L1.2, otherwise this field is of type RsvdP.This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear.The Port behavior is undefined if this field is modified when either the ASPM L1.2 Enable and/or PCI-PM L1.2 Enable bit(s) are Set.Note: The access attributes of this field are as follows: - Wire: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP - Dbi: L1SUB_CAPABILITY_REG.L1_2_ASPM_SUPPORT||L1SUB_CAPABILITY_REG.L1_2_PCIPM_SUPPORT ? RWS : RSVDP 730x05R/WRSVDP_8DBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_WIDTHDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_MSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_LSBDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_RANGEDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_RESETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_GETDBI_SLAVE_PF0_L1SUB_CAP_L1SUB_CONTROL2_REG_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr35095Reserved for future use.3180x000000RgroupDBI_Slave.PF0_LNR_CAPPF0_LNR_CAPDBI_SLAVE_PF0_LNR_CAP_ADDRESSDBI_SLAVE_PF0_LNR_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_LNR_CAP_OFFSETDBI_SLAVE_PF0_LNR_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr352730x2BCR/WDBI_Slave_PF0_LNR_CAPPF LNR Capability StructureregisterDBI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFFregisterDBI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFFregisterDBI_Slave.PF0_LNR_CAP.LNR_EXT_CAP_HDR_OFFLNR_EXT_CAP_HDR_OFFDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_ADDRESSDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_OFFSETDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr351560x0R0x2c41001cDBI_Slave_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFFLNR Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseLNR_EXT_CAP_IDDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_WIDTHDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_MSBDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_LSBDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_RANGEDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_RESETDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_GETDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_EXT_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr35123PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x001cRLNR_CAP_VERSIONDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_WIDTHDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_MSBDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_LSBDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_RANGEDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_RESETDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_FIELD_MASKDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_GETDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr35139Capability Verison.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RLNR_NEXT_OFFSETDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_MSBDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_LSBDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_RESETDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_GETDBI_SLAVE_PF0_LNR_CAP_LNR_EXT_CAP_HDR_OFF_LNR_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr35155Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x2c4RregisterDBI_Slave.PF0_LNR_CAP.LNR_CAP_CONTROL_OFFLNR_CAP_CONTROL_OFFDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_ADDRESSDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_OFFSETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr352720x4R/W0x1f000000DBI_Slave_PF0_LNR_CAP_LNR_CAP_CONTROL_OFFLNR Control Register and Capability Register.For a description of this standard PCIe register, see the PCI Express Base Specification.falsefalsefalsefalseLNR_64_SUPPORTEDDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_WIDTHDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_MSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_LSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_RANGEDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_RESETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_FIELD_MASKDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_GETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_64_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr35178LNR-64 Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.000x0RLNR_128_SUPPORTEDDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_WIDTHDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_MSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_LSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_RANGEDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_RESETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_FIELD_MASKDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_GETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_128_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr35195LNR-128 Supported.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.110x0RRSVDP_2DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_WIDTHDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_MSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_LSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_RANGEDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_RESETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_FIELD_MASKDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_GETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr35203Reserved for future use.720x00RLNR_REGISTRATION_MAXDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_WIDTHDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_MSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_LSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_RANGEDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_RESETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_FIELD_MASKDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_GETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_MAX_SETDWC_pcie_wire_cpcie_usp_4x8.csr35220LNR Registration Max.For a description of this standard PCIe register field, see the PCI Express Base Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1280x00RRSVDP_13DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_WIDTHDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_MSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_LSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_RANGEDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_RESETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_FIELD_MASKDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_GETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_13_SETDWC_pcie_wire_cpcie_usp_4x8.csr35228Reserved for future use.15130x0RLNR_ENABLEDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_WIDTHDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_MSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_LSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_RANGEDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_RESETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_FIELD_MASKDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_GETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr35237LNR Enable.For a description of this standard PCIe register field, see the PCI Express Base Specification.16160x0R/WLNR_CLSDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_WIDTHDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_MSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_LSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_RANGEDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_RESETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_FIELD_MASKDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_GETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_CLS_SETDWC_pcie_wire_cpcie_usp_4x8.csr35246LNR CLS.For a description of this standard PCIe register field, see the PCI Express Base Specification.17170x0R/WRSVDP_18DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_WIDTHDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_MSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_LSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_RANGEDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_RESETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_FIELD_MASKDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_GETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr35254Reserved for future use.23180x00RLNR_REGISTRATION_LIMITDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_WIDTHDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_MSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_LSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_RANGEDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_RESETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_FIELD_MASKDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_GETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_LNR_REGISTRATION_LIMIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr35263LNR Registration Limit.For a description of this standard PCIe register field, see the PCI Express Base Specification.28240x1fR/WRSVDP_29DBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_WIDTHDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_MSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_LSBDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_RANGEDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_RESETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_FIELD_MASKDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_GETDBI_SLAVE_PF0_LNR_CAP_LNR_CAP_CONTROL_OFF_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr35271Reserved for future use.31290x0RgroupDBI_Slave.PF0_RAS_DES_CAPPF0_RAS_DES_CAPDBI_SLAVE_PF0_RAS_DES_CAP_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr385130x2C4R/WDBI_Slave_PF0_RAS_DES_CAPRAS D.E.S. Capability Structure (VSEC)registerDBI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGregisterDBI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGregisterDBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGregisterDBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGregisterDBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGregisterDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGregisterDBI_Slave.PF0_RAS_DES_CAP.RAS_DES_CAP_HEADER_REGRAS_DES_CAP_HEADER_REGDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr353320x0R0x3c41000bDBI_Slave_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REGVendor-Specific Extended Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseEXTENDED_CAP_IDDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_MSBDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_LSBDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_RESETDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_GETDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr35299PCI Express Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x000bRCAP_VERSIONDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_MSBDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_LSBDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_RESETDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_GETDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr35315Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_MSBDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_LSBDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_RESETDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_GETDBI_SLAVE_PF0_RAS_DES_CAP_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr35331Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x3c4RregisterDBI_Slave.PF0_RAS_DES_CAP.VENDOR_SPECIFIC_HEADER_REGVENDOR_SPECIFIC_HEADER_REGDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr353660x4R0x10040002DBI_Slave_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REGVendor-Specific Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVSEC_IDDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_MSBDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_LSBDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_RESETDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_GETDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr35347VSEC ID.For a description of this standard PCIe register field, see the PCI Express Specification.1500x0002RVSEC_REVDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_MSBDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_LSBDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_RESETDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_GETDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_SETDWC_pcie_wire_cpcie_usp_4x8.csr35356VSEC Rev.For a description of this standard PCIe register field, see the PCI Express Specification.19160x4RVSEC_LENGTHDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_MSBDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_LSBDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_RESETDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_GETDBI_SLAVE_PF0_RAS_DES_CAP_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr35365VSEC Length.For a description of this standard PCIe register field, see the PCI Express Specification.31200x100RregisterDBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_CONTROL_REGEVENT_COUNTER_CONTROL_REGDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr355130x8R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REGEvent Counter Control.This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG viewport register. - Setting the EVENT_COUNTER_ENABLE field in this register enables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Setting the EVENT_COUNTER_CLEAR field in this register clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Reading the EVENT_COUNTER_STATUS field in this register returns the Enable status of the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.falsefalsefalsefalseEVENT_COUNTER_CLEARDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_GETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_SETDWC_pcie_wire_cpcie_usp_4x8.csr35407Event Counter Clear.Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.You can clear the value of a specific Event Counter by writing the 'per clear' code and you can clear all event counters at once by writing the 'all clear' code.The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11: all clear - Other: reserved100x0WEVENT_COUNTER_ENABLEDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr35433Event Counter Enable.Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.By default, all event counters are disabled.You can enable/disable a specific Event Counter by writing the 'per event off' or 'per event on' codes.You can enable/disable all event counters by writing the 'all on' or 'all off' codes.The read value is always '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no change - 101: all off - 110: no change - 111: all on420x0WRSVDP_5DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_GETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr35441Reserved for future use.650x0REVENT_COUNTER_STATUSDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_GETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr35456Event Counter Status.This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECTNote: This register field is sticky.770x0REVENT_COUNTER_LANE_SELECTDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_GETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr35473Event Counter Lane Select.This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.1180x0R/WRSVDP_12DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_GETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr35481Reserved for future use.15120x0REVENT_COUNTER_EVENT_SELECTDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_GETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr35504Event Counter Data Select.This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the GroupFor example: - 0x000: Ebuf Overflow - 0x001: Ebuf Underrun - .. - 0x700: Tx Memory Write - 0x713: Rx Message TLPFor detailed definitions of Group number and Event number, see the RAS DES chapter in the Databook.Note: This register field is sticky.27160x000R/WRSVDP_28DBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_GETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_CONTROL_REG_RSVDP_28_SETDWC_pcie_wire_cpcie_usp_4x8.csr35512Reserved for future use.31280x0RregisterDBI_Slave.PF0_RAS_DES_CAP.EVENT_COUNTER_DATA_REGEVENT_COUNTER_DATA_REGDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr355380xCR0x00000000DBI_Slave_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REGEvent Counter Data.This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REGFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEVENT_COUNTER_DATADBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_GETDBI_SLAVE_PF0_RAS_DES_CAP_EVENT_COUNTER_DATA_REG_EVENT_COUNTER_DATA_SETDWC_pcie_wire_cpcie_usp_4x8.csr35537Event Counter Data.This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REGNote: This register field is sticky.3100x00000000RregisterDBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_CONTROL_REGTIME_BASED_ANALYSIS_CONTROL_REGDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr356540x10R/W0x00000100DBI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REGTime-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIMER_STARTDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_MSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_LSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_RESETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_GETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_SETDWC_pcie_wire_cpcie_usp_4x8.csr35562Timer Start. - 1: Start/Restart - 0: StopThis bit will be cleared automatically when the measurement is finished.Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop.Note: This register field is sticky.000x0R/WRSVDP_1DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_MSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_LSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_RESETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_GETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr35570Reserved for future use.710x00RTIME_BASED_DURATION_SELECTDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_GETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr35592Time-based Duration Select.Selects the duration of time-based analysis.When "manual control" is selected and TIMER_START is set to '1', this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1: 1ms - 0x2: 10ms - 0x3: 100ms - 0x4: 1s - 0x5: 2s - 0x6: 4s - 0xff: 4us (Debug purpose) - Else: ReservedNote: This register field is sticky.1580x01R/WRSVDP_16DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_MSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_LSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_RESETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_GETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr35600Reserved for future use.23160x00RTIME_BASED_REPORT_SELECTDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_GETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr35653Time-based Report Select.Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT), and returned in TIME_BASED_ANALYSIS_DATA.Each type of data is measured using one of three types of units: - Core_clk Cycles for 2.5GT/s, 5.0GT/s, 8.0GT/s, 16.0GT/s, 32GT/s. Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x00] * TIME_BASED_ANALYSIS_DATA - Aux_clk Cycles. Total time in ps is [Period of platform specific clock] * TIME_BASED_ANALYSIS_DATA - Core_clk Cycles for 20GT/s, 25GT/s (CCIX ESM data rate). Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x10] * TIME_BASED_ANALYSIS_DATA - Data Bytes. Actual amount of bytes is 16 * TIME_BASED_ANALYSIS_DATACore_clk Cycles for 2.5GT/s, 5.0GT/s, 8.0GT/s, 16.0GT/s, 32GT/s - 0x00: Duration of 1 cycle - 0x01: TxL0s - 0x02: RxL0s - 0x03: L0 - 0x04: L1 - 0x07: Configuration/Recovery - 0x08: TxL0s and RxL0sAux_clk Cycles - 0x05: L1.1 - 0x06: L1.2 - 0x09: L1 auxCore_clk Cycles for 20GT/s, 25GT/s (CCIX ESM data rate) - 0x10: Duration of 1 cycle - 0x11: TxL0s - 0x12: RxL0s - 0x13: L0 - 0x14: L1 - 0x17: Configuration/Recovery - 0x18: TxL0s and RxL0sData Bytes - 0x20: Tx PCIe TLP data payload Bytes - 0x21: Rx PCIe TLP data payload Bytes - 0x22: Tx CCIX TLP data payload Bytes - 0x23: Rx CCIX TLP data payload Bytes - Else: RsvdNote: This register field is sticky.31240x00R/WregisterDBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_REGTIME_BASED_ANALYSIS_DATA_REGDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr356810x14R0x00000000DBI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REGTime-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state.This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIME_BASED_ANALYSIS_DATADBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_MSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_LSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_RESETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_GETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_REG_TIME_BASED_ANALYSIS_DATA_SETDWC_pcie_wire_cpcie_usp_4x8.csr35680Time Based Analysis Data.This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.The results are cleared when next measurement starts.Note: This register field is sticky.3100x00000000RregisterDBI_Slave.PF0_RAS_DES_CAP.TIME_BASED_ANALYSIS_DATA_63_32_REGTIME_BASED_ANALYSIS_DATA_63_32_REGDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr357020x18R0x00000000DBI_Slave_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REGUpper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTIME_BASED_ANALYSIS_DATA_63_32DBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_MSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_LSBDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_RESETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_GETDBI_SLAVE_PF0_RAS_DES_CAP_TIME_BASED_ANALYSIS_DATA_63_32_REG_TIME_BASED_ANALYSIS_DATA_63_32_SETDWC_pcie_wire_cpcie_usp_4x8.csr35701Upper 32 bits of Time Based Analysis Data.Note: This register field is sticky.3100x00000000RregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ_ENABLE_REGEINJ_ENABLE_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr358390x30R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ_ENABLE_REGError Injection Enable.Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1: Sequence Number Error: EINJ1_SEQNUM_REG - 2: DLLP Error: EINJ2_DLLP_REG - 3: Symbol DataK Mask Error or Sync Header Error: EINJ3_SYMBOL_REG - 4: FC Credit Update Error: EINJ4_FC_REG - 5: TLP Duplicate/Nullify Error: EINJ5_SP_TLP_REG - 6: Specific TLP Error: EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REGAfter the errors have been inserted by controller, it will clear each bit here.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_INJECTION0_ENABLEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr35735Error Injection0 Enable (CRC Error).Enables insertion of errors into various CRC.For more details, see the EINJ0_CRC_REG register.Note: This register field is sticky.000x0R/WERROR_INJECTION1_ENABLEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr35749Error Injection1 Enable (Sequence Number Error).Enables insertion of errors into sequence numbers.For more details, see the EINJ1_SEQNUM_REG register.Note: This register field is sticky.110x0R/WERROR_INJECTION2_ENABLEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr35763Error Injection2 Enable (DLLP Error).Enables insertion of DLLP errors.For more details, see the EINJ2_DLLP_REG register.Note: This register field is sticky.220x0R/WERROR_INJECTION3_ENABLEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr35779Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error).Enables DataK masking of special symbols or the breaking of the sync header.For more details, see the EINJ3_SYMBOL_REG register.Note: This register field is sticky.330x0R/WERROR_INJECTION4_ENABLEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr35793Error Injection4 Enable (FC Credit Update Error).Enables insertion of errors into UpdateFCs.For more details, see the EINJ4_FC_REG register.Note: This register field is sticky.440x0R/WERROR_INJECTION5_ENABLEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr35807Error Injection5 Enable (TLP Duplicate/Nullify Error).Enables insertion of duplicate/nullified TLPs.For more details, see the EINJ5_SP_TLP_REG register.Note: This register field is sticky.550x0R/WERROR_INJECTION6_ENABLEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr35830Error Injection6 Enable (Specific TLP Error).Enables insertion of errors into the packets that you select.You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT =0.You can set this bit to '1' when you have disabled the address translation by setting ADDR_TRANSLATION_SUPPORT_EN=0.For more details, see the EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG registers.Note: This register field is sticky.660x0R/WRSVDP_7DBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ_ENABLE_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr35838Reserved for future use.3170x0000000RregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ0_CRC_REGEINJ0_CRC_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr359090x34R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ0_CRC_REGError Injection Control 0 (CRC Error).Controls the insertion of errors into the CRC, and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link Retry starts. - 16-bit CRC of ACK/NAK DLLPs. Bad DLLP occurs at the receiver side; Replay NUM Rollover occurs. - 16-bit CRC of UpdateFC DLLPs. Error insertion continues for the specific time; LTSSM transitions to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - ECRC. If ECRC check is enabled, ECRC error is detected at the receiver side. - FCRC. Framing error will be detected, TLP is discarded, and the LTSSM transitions to Recovery state. - Parity of TSOS. Error insertion continues for the specific time; LTSSM Recovery/Configuration timeout will occur. - Parity of SKPOS. Lane error will be detected at the receiver side.falsefalsefalsefalseEINJ0_COUNTDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr35877Error injection count.Indicates the number of errors.This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the counter value is 0x00 and ERROR_INJECTION0_ENABLE=1, the errors are inserted until ERROR_INJECTION0_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ0_CRC_TYPEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_EINJ0_CRC_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr35900Error injection type.Selects the type of CRC error to be inserted.Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC error injection - 0100b: TLP's FCRC error injection (128b/130b) - 0101b: Parity error of TSOS (128b/130b) - 0110b: Parity error of SKPOS (128b/130b)Rx Path - 1000b: LCRC error injection - 1011b: ECRC error injection - Others: ReservedNote: This register field is sticky.1180x0R/WRSVDP_12DBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ0_CRC_REG_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr35908Reserved for future use.31120x00000RregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ1_SEQNUM_REGEINJ1_SEQNUM_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr360070x38R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REGError Injection Control 1 (Sequence Number Error).Controls the sequence number of the specific TLPs and ACK/NAK DLLPs.Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: - ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 4096 >= 2048TLP is treated as Duplicate TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ - (NEXT_RCV_SEQ - Sequence Number) mod 4096 <= 2048TLP is treated as Bad TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ and - (NEXT_RCV_SEQ - Sequence Number) mod 4096 > 2048falsefalsefalsefalseEINJ1_COUNTDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr35944Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION1_ENABLE=1, the errors are inserted until ERROR_INJECTION1_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ1_SEQNUM_TYPEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr35956Sequence number type.Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# ErrorNote: This register field is sticky.880x0R/WRSVDP_9DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr35964Reserved for future use.1590x00REINJ1_BAD_SEQNUMDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_SETDWC_pcie_wire_cpcie_usp_4x8.csr35998Bad sequence number.Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095For example: - Set Type, SEQ# and Count -- EINJ1_SEQNUM_TYPE =0 (Insert errors into new TLPs) -- EINJ1_BAD_SEQNUM =0x1FFD (represents -3) -- EINJ1_COUNT =1 - Enable Error Injection -- ERROR_INJECTION1_ENABLE =1 - Send a TLP From the Core's Application Interface -- Assume SEQ#5 is given to the TLP. - The SEQ# is Changed to #2 by the Error Injection Function in Layer2. -- 5 + (-3) = 2 - The TLP with SEQ#2 is Transmitted to PCIe Link.Note: This register field is sticky.28160x0000R/WRSVDP_29DBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ1_SEQNUM_REG_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr36006Reserved for future use.31290x0RregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ2_DLLP_REGEINJ2_DLLP_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr360670x3CR/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ2_DLLP_REGError Injection Control 2 (DLLP Error).Controls the transmission of DLLPs and inserts the following errors: - If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the transmitter of the TLPs and then Data Link Retry will occur. - If "Update FC DLLP's transmission block" is selected, LTSSM will transition to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - If "Always Transmission for NAK DLLP" is selected, Data Link Retry will occur at the transmitter of the TLPs. Furthermore, Replay NUM Rollover will occur when the transmitter has been requested four times to send the TLP with the same sequence number.falsefalsefalsefalseEINJ2_COUNTDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr36044Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION2_ENABLE =1, the errors are inserted until ERROR_INJECTION2_ENABLE is set to '0'.This register is affected only when EINJ2_DLLP_TYPE =2'10b.Note: This register field is sticky.700x00R/WEINJ2_DLLP_TYPEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr36058DLLP Type.Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: ReservedNote: This register field is sticky.980x0R/WRSVDP_10DBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ2_DLLP_REG_RSVDP_10_SETDWC_pcie_wire_cpcie_usp_4x8.csr36066Reserved for future use.31100x000000RregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ3_SYMBOL_REGEINJ3_SYMBOL_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr361270x40R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REGError Injection Control 3 (Symbol Error).When 8b/10b encoding is used, this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeout of the LTSSM. - If END/EDB/STP/SDP is selected, TLP/DLLP will be discarded at the receiver side.When 128b/130b encoding is used, this register controls error insertion into the sync-header.falsefalsefalsefalseEINJ3_COUNTDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr36095Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION3_ENABLE =1, the errors are inserted until ERROR_INJECTION3_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ3_SYMBOL_TYPEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr36118Error Type.8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set) - 011b: COM/FTS(FTS Order set) - 100b: COM/IDL(E-Idle Order set) - 101b: END/EDB Symbol - 110b: STP/SDP Symbol - 111b: COM/SKP(SKP Order set)128b/130b encoding - Change sync header. - 000b: Invert sync header - Others: ReservedNote: This register field is sticky.1080x0R/WRSVDP_11DBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ3_SYMBOL_REG_RSVDP_11_SETDWC_pcie_wire_cpcie_usp_4x8.csr36126Reserved for future use.31110x000000RregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ4_FC_REGEINJ4_FC_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr362320x44R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ4_FC_REGError Injection Control 4 (FC Credit Error).Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Posted TLP Data credit - Non-Posted TLP Data credit - Completion TLP Data creditThese errors are not correctable while error insertion is enabled. Receiver buffer overflow error might occur.falsefalsefalsefalseEINJ4_COUNTDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr36158Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION4_ENABLE =1, the errors are inserted until ERROR_INJECTION4_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ4_UPDFC_TYPEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr36176Update-FC type.Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit value control - 101b: Non-Posted TLP Data Credit value control - 110b: Completion TLP Data Credit value control - 111b: ReservedNote: This register field is sticky.1080x0R/WRSVDP_11DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_11_SETDWC_pcie_wire_cpcie_usp_4x8.csr36184Reserved for future use.11110x0REINJ4_VC_NUMBERDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_VC_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr36195VC Number.Indicates target VC Number.Note: This register field is sticky.14120x0R/WRSVDP_15DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr36203Reserved for future use.15150x0REINJ4_BAD_UPDFC_VALUEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr36223Bad update-FC credit value.Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095Note: This register field is sticky.28160x0000R/WRSVDP_29DBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ4_FC_REG_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr36231Reserved for future use.31290x0RregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ5_SP_TLP_REGEINJ5_SP_TLP_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr362890x48R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REGError Injection Control 5 (Specific TLP Error).Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP, the controller initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TLPs will be duplicate TLPs at the receiver side. - For Nullified TLP, the TLPs that the controller transmits are changed into nullified TLPs and the original TLPs are stored in the retry buffer. The receiver of these TLPs will detect the lack of seq# and send NAK DLLP at the next TLP. Then the original TLPs are sent from retry buffer and the data controls are recovered. For 128 bit controller or more than 128 bit, the controller inserts errors the number of times of EINJ5_COUNT but doesn't ensure that the errors are continuously inserted into TLPs.falsefalsefalsefalseEINJ5_COUNTDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr36266Error injection count.Indicates the number of errors.This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION5_ENABLE =1, the errors are inserted until ERROR_INJECTION5_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ5_SPECIFIED_TLPDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_SETDWC_pcie_wire_cpcie_usp_4x8.csr36280Specified TLP.Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer).Note: This register field is sticky.880x0R/WRSVDP_9DBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ5_SP_TLP_REG_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr36288Reserved for future use.3190x000000RregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H0_REGEINJ6_COMPARE_POINT_H0_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr363270x4CR/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REGError Injection Control 6 (Compare Point Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H0DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H0_REG_EINJ6_COMPARE_POINT_H0_SETDWC_pcie_wire_cpcie_usp_4x8.csr36326Packet Compare Point: 1st DWORD.Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H1_REGEINJ6_COMPARE_POINT_H1_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr363650x50R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REGError Injection Control 6 (Compare Point Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H1DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H1_REG_EINJ6_COMPARE_POINT_H1_SETDWC_pcie_wire_cpcie_usp_4x8.csr36364Packet Compare Point: 2nd DWORD.Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H2_REGEINJ6_COMPARE_POINT_H2_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr364010x54R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REGError Injection Control 6 (Compare Point Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H2DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H2_REG_EINJ6_COMPARE_POINT_H2_SETDWC_pcie_wire_cpcie_usp_4x8.csr36400Packet Compare Point: 3rd DWORD.Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_POINT_H3_REGEINJ6_COMPARE_POINT_H3_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr364390x58R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REGError Injection Control 6 (Compare Point Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_POINT_H3DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_POINT_H3_REG_EINJ6_COMPARE_POINT_H3_SETDWC_pcie_wire_cpcie_usp_4x8.csr36438Packet Compare Point: 4th DWORD.Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H0_REGEINJ6_COMPARE_VALUE_H0_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr364730x5CR/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REGError Injection Control 6 (Compare Value Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H0DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H0_REG_EINJ6_COMPARE_VALUE_H0_SETDWC_pcie_wire_cpcie_usp_4x8.csr36472Packet Compare Value: 1st DWORD.Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H1_REGEINJ6_COMPARE_VALUE_H1_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr365070x60R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REGError Injection Control 6 (Compare Value Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H1DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H1_REG_EINJ6_COMPARE_VALUE_H1_SETDWC_pcie_wire_cpcie_usp_4x8.csr36506Packet Compare Value: 2nd DWORD.Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H2_REGEINJ6_COMPARE_VALUE_H2_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr365410x64R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REGError Injection Control 6 (Compare Value Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H2DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H2_REG_EINJ6_COMPARE_VALUE_H2_SETDWC_pcie_wire_cpcie_usp_4x8.csr36540Packet Compare Value: 3rd DWORD.Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_COMPARE_VALUE_H3_REGEINJ6_COMPARE_VALUE_H3_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr365750x68R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REGError Injection Control 6 (Compare Value Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the EINJ6_TLP_REG register.falsefalsefalsefalseEINJ6_COMPARE_VALUE_H3DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_COMPARE_VALUE_H3_REG_EINJ6_COMPARE_VALUE_H3_SETDWC_pcie_wire_cpcie_usp_4x8.csr36574Packet Compare Value: 4th DWORD.Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*).Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H0_REGEINJ6_CHANGE_POINT_H0_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr366070x6CR/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REGError Injection Control 6 (Change Point Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H0DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H0_REG_EINJ6_CHANGE_POINT_H0_SETDWC_pcie_wire_cpcie_usp_4x8.csr36606Packet Change Point: 1st DWORD.Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H1_REGEINJ6_CHANGE_POINT_H1_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr366390x70R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REGError Injection Control 6 (Change Point Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H1DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H1_REG_EINJ6_CHANGE_POINT_H1_SETDWC_pcie_wire_cpcie_usp_4x8.csr36638Packet Change Point: 2nd DWORD.Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H2_REGEINJ6_CHANGE_POINT_H2_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr366710x74R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REGError Injection Control 6 (Change Point Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H2DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H2_REG_EINJ6_CHANGE_POINT_H2_SETDWC_pcie_wire_cpcie_usp_4x8.csr36670Packet Change Point: 3rd DWORD.Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_POINT_H3_REGEINJ6_CHANGE_POINT_H3_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr367030x78R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REGError Injection Control 6 (Change Point Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_POINT_H3DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_POINT_H3_REG_EINJ6_CHANGE_POINT_H3_SETDWC_pcie_wire_cpcie_usp_4x8.csr36702Packet Change Point: 4th DWORD.Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H0_REGEINJ6_CHANGE_VALUE_H0_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr367380x7CR/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REGError Injection Control 6 (Change Value Header DWORD #0).Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H0DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H0_REG_EINJ6_CHANGE_VALUE_H0_SETDWC_pcie_wire_cpcie_usp_4x8.csr36737Packet Change Value: 1st DWORD.Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H1_REGEINJ6_CHANGE_VALUE_H1_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr367730x80R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REGError Injection Control 6 (Change Value Header DWORD #1).Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H1DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H1_REG_EINJ6_CHANGE_VALUE_H1_SETDWC_pcie_wire_cpcie_usp_4x8.csr36772Packet Change Value: 2nd DWORD.Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H2_REGEINJ6_CHANGE_VALUE_H2_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr368080x84R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REGError Injection Control 6 (Change Value Header DWORD #2).Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H2DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H2_REG_EINJ6_CHANGE_VALUE_H2_SETDWC_pcie_wire_cpcie_usp_4x8.csr36807Packet Change Value: 3rd DWORD.Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_CHANGE_VALUE_H3_REGEINJ6_CHANGE_VALUE_H3_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr368430x88R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REGError Injection Control 6 (Change Value Header DWORD #3).Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register.Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.falsefalsefalsefalseEINJ6_CHANGE_VALUE_H3DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_CHANGE_VALUE_H3_REG_EINJ6_CHANGE_VALUE_H3_SETDWC_pcie_wire_cpcie_usp_4x8.csr36842Packet Change Value: 4th DWORD.Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*).Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_RAS_DES_CAP.EINJ6_TLP_REGEINJ6_TLP_REGDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr369240x8CR/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_EINJ6_TLP_REGError Injection Control 6 (Packet Error).The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP.The type and number of errors are specified by the this register.The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the this register.Only applies when EINJ6_INVERTED_CONTROL in this register =0.The TLP into that errors are injected will not arrive at the transaction layer of the remote device when all of the following conditions are true. - Using 128b/130b encoding - Injecting errors into TLP Length field / TLP digest bitfalsefalsefalsefalseEINJ6_COUNTDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr36887Error Injection Count.Indicates the number of errors to insert.This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION6_ENABLE=1, errors are inserted until ERROR_INJECTION6_ENABLE is set to '0'. Note: This register field is sticky.700x00R/WEINJ6_INVERTED_CONTROLDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_SETDWC_pcie_wire_cpcie_usp_4x8.csr36900Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3].Note: This register field is sticky.880x0R/WEINJ6_PACKET_TYPEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr36915Packet type.Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: ReservedNote: This register field is sticky.1190x0R/WRSVDP_12DBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_MSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_LSBDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_RESETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_GETDBI_SLAVE_PF0_RAS_DES_CAP_EINJ6_TLP_REG_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr36923Reserved for future use.31120x00000RregisterDBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL1_REGSD_CONTROL1_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr370210xA0R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_SD_CONTROL1_REGSilicon Debug Control 1.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_DETECT_LANEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_SETDWC_pcie_wire_cpcie_usp_4x8.csr36947Force Detect Lane.When the FORCE_DETECT_LANE_EN field is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15Note: This register field is sticky.1500x0000R/WFORCE_DETECT_LANE_ENDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr36961Force Detect Lane Enable.When this bit is set, the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE.Note: This register field is sticky.16160x0R/WRSVDP_17DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_17_SETDWC_pcie_wire_cpcie_usp_4x8.csr36969Reserved for future use.19170x0RTX_EIOS_NUMDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_TX_EIOS_NUM_SETDWC_pcie_wire_cpcie_usp_4x8.csr36994Number of Tx EIOS.This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification.2.5GT/s, 8.0GT/s or higher: - 0x0: 1 - 0x1: 4 - 0x2: 8 - 0x3: 165.0GT/s: - 0x0: 2 - 0x1: 8 - 0x2: 16 - 0x3: 32Note: This register field is sticky.21200x0R/WLOW_POWER_INTERVALDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_LOW_POWER_INTERVAL_SETDWC_pcie_wire_cpcie_usp_4x8.csr37012Low Power Entry Interval Time.Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - 0x3: 640nsNote: This register field is sticky.23220x0R/WRSVDP_24DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL1_REG_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr37020Reserved for future use.31240x00RregisterDBI_Slave.PF0_RAS_DES_CAP.SD_CONTROL2_REGSD_CONTROL2_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr371440xA4R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_SD_CONTROL2_REGSilicon Debug Control 2.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseHOLD_LTSSMDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_HOLD_LTSSM_SETDWC_pcie_wire_cpcie_usp_4x8.csr37039Hold and Release LTSSM.For as long as this register is '1', the controller stays in the current LTSSM.Note: This register field is sticky.000x0R/WRECOVERY_REQUESTDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RECOVERY_REQUEST_SETDWC_pcie_wire_cpcie_usp_4x8.csr37052Recovery Request.When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization.110x0WNOACK_FORCE_LINKDOWNDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_SETDWC_pcie_wire_cpcie_usp_4x8.csr37066Force LinkDown.When this bit is set and the controller detects REPLY_NUM rolling over 4 times, the LTSSM transitions to Detect State.Note: This register field is sticky.220x0R/WRSVDP_3DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr37074Reserved for future use.730x00RDIRECT_RECIDLE_TO_CONFIGDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_SETDWC_pcie_wire_cpcie_usp_4x8.csr37087Direct Recovery.Idle to Configuration.When this bit is set and the LTSSM is in Recovery Idle State, the LTSSM transitions to Configuration state.Note: This register field is sticky.880x0R/WDIRECT_POLCOMP_TO_DETECTDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr37100Direct Polling.Compliance to Detect.When this bit is set and the LTSSM is in Polling Compliance State, the LTSSM transitions to Detect state.Note: This register field is sticky.990x0R/WDIRECT_LPBKSLV_TO_EXITDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_DIRECT_LPBKSLV_TO_EXIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr37114Direct Loopback Slave To Exit.When this bit is set and the LTSSM is in Loopback Slave Active State, the LTSSM transitions to Loopback Slave Exit state.Note: This register field is sticky.10100x0R/WRSVDP_11DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_11_SETDWC_pcie_wire_cpcie_usp_4x8.csr37122Reserved for future use.15110x00RFRAMING_ERR_RECOVERY_DISABLEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr37135Framing Error Recovery Disable.This bit disables a transition to Recovery state when a Framing Error is occurred.Note: This register field is sticky.16160x0R/WRSVDP_17DBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_CONTROL2_REG_RSVDP_17_SETDWC_pcie_wire_cpcie_usp_4x8.csr37143Reserved for future use.31170x0000RregisterDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LANE_REGSD_STATUS_L1LANE_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr372760xB0R/W0x00180000DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REGSilicon Debug Status(Layer1 Per-lane).This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REGFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseLANE_SELECTDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_LANE_SELECT_SETDWC_pcie_wire_cpcie_usp_4x8.csr37169Lane Select.Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.300x0R/WRSVDP_4DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr37177Reserved for future use.1540x000RPIPE_RXPOLARITYDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_SETDWC_pcie_wire_cpcie_usp_4x8.csr37192PIPE:RxPolarity.Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT).Note: This register field is sticky.16160x0RPIPE_DETECT_LANEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_SETDWC_pcie_wire_cpcie_usp_4x8.csr37207PIPE:Detect Lane.Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT).Note: This register field is sticky.17170x0RPIPE_RXVALIDDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXVALID_SETDWC_pcie_wire_cpcie_usp_4x8.csr37222PIPE:RxValid.Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT).Note: This register field is sticky.18180x0RPIPE_RXELECIDLEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr37237PIPE:RxElecIdle.Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT).Note: This register field is sticky.19190x1RPIPE_TXELECIDLEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr37252PIPE:TxElecIdle.Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT).Note: This register field is sticky.20200x1RRSVDP_21DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_RSVDP_21_SETDWC_pcie_wire_cpcie_usp_4x8.csr37260Reserved for future use.23210x0RDESKEW_POINTERDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LANE_REG_DESKEW_POINTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr37275Deskew Pointer.Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT).Note: This register field is sticky.31240x00RregisterDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L1LTSSM_REGSD_STATUS_L1LTSSM_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr374250xB4R/W0x00000200DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REGSilicon Debug Status(Layer1 LTSSM).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFRAMING_ERR_PTRDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_SETDWC_pcie_wire_cpcie_usp_4x8.csr37345First Framing Error Pointer.Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1.Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When current token was not a valid EDB token and previous token was an EDB. (128/256 bit controller only) - 03h: When SDP token was received but not expected. (128 bit & (x8 | x16) controller only) - 04h: When STP token was received but not expected. (128 bit & (x8 | x16) controller only) - 05h: When EDS token was expected but not received or whenever an EDS token was received but not expected. - 06h: When a framing error was detected in the deskew block while a packet has been in progress in token_finder.Received Unexpected STP Token - 11h: When Framing CRC in STP token did not match - 12h: When Framing Parity in STP token did not match. - 13h: When Framing TLP Length in STP token was smaller than 5 DWORDs.Received Unexpected Block - 21h: When Receiving an OS Block following SDS in Datastream state - 22h: When Data Block followed by OS Block different from SKP, EI, EIE in Datastream state - 23h: When Block with an undefined Block Type in Datastream state - 24h: When Data Stream without data over three cycles in Datastream state - 25h: When OS Block during Data Stream in Datastream state - 26h: When RxStatus Error was detected in Datastream state - 27h: When Not all active lanes receiving SKP OS starting at same cycle time in SKPOS state - 28h: When a 2-Block timeout occurs for SKP OS in SKPOS state - 29h: When Receiving consecutive OS Blocks within a Data Stream in SKPOS state - 2Ah: When Phy status error was detected in SKPOS state - 2Bh: When Not all active lanes receiving EIOS starting at same cycle time in EIOS state - 2Ch: When At least one Symbol from the first 4 Symbols is not EIOS Symbol in EIOS state (CX_NB=2 only) - 2Dh: When Not all active lanes receiving EIEOS starting at same cycle time in EIEOS state - 2Eh: When Not full 16 eieos symbols are received in EIEOS stateAll other values not listed above are Reserved.Note: This register field is sticky.600x00RFRAMING_ERRDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_SETDWC_pcie_wire_cpcie_usp_4x8.csr37356Framing Error.Indicates Framing Error detection status.770x0R/W1CPIPE_POWER_DOWNDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_SETDWC_pcie_wire_cpcie_usp_4x8.csr37370PIPE:PowerDown.Indicates PIPE PowerDown signal.Note: This register field is sticky.1080x2RRSVDP_11DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_RSVDP_11_SETDWC_pcie_wire_cpcie_usp_4x8.csr37378Reserved for future use.14110x0RLANE_REVERSALDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_SETDWC_pcie_wire_cpcie_usp_4x8.csr37394Lane Reversal Operation.Receiver detected lane reversal.This field is only valid in the L0 LTSSM state.Note: This register field is sticky.15150x0RLTSSM_VARIABLEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr37424LTSSM Variable.Indicates internal LTSSM variables defined in the PCI Express Base Specification.C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if both ports advertised the UpConfigure capability in the last Config.Complete. - 4: select_deemphasis - 5: start_equalization_w_preset - 6: equalization_done_8GT_data_rate - 7: equalization_done_16GT_data_rate - 15:8: idle_to_rlock_transitionedM-PCIe Mode: - 0: idle_to_recovery - 1: recovery_to_configurationNote: This register field is sticky.31160x0000RregisterDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_PM_REGSD_STATUS_PM_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr375660xB8R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_PM_REGSilicon Debug Status(PM).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseINTERNAL_PM_MSTATEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_SETDWC_pcie_wire_cpcie_usp_4x8.csr37467Internal PM State(Master).Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah: L1_WAIT_LAST_TLP_ACK - 0Bh: L1_WAIT_PMDLLP_ACK - 0Ch: L1_LINK_ENTR_L1 - 0Dh: L1_EXIT - 0Fh: PREP_4L1 - 10h: L23_BLOCK_TLP - 11h: L23_WAIT_LAST_TLP_ACK - 12h: L23_WAIT_PMDLLP_ACK - 13h: L23_ENTR_L23 - 14h: L23RDY - 15h: PREP_4L23 - 16h: L23RDY_WAIT4ALIVE - 17h: L0S_BLOCK_TLP - 18h: WAIT_LAST_PMDLLP - 19h: WAIT_DSTATE_UPDATENote: This register field is sticky.400x00RRSVDP_5DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr37475Reserved for future use.750x0RINTERNAL_PM_SSTATEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_SETDWC_pcie_wire_cpcie_usp_4x8.csr37502Internal PM State(Slave).Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h: S_L1_EXIT - 8h: S_L23RDY - 9h: S_LINK_ENTR_L23 - Ah: S_L23RDY_WAIT4ALIVE - Bh: S_ACK_WAIT4IDLE - Ch: S_WAIT_LAST_PMDLLPNote: This register field is sticky.1180x0RPME_RESEND_FLAGDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_PME_RESEND_FLAG_SETDWC_pcie_wire_cpcie_usp_4x8.csr37516PME Re-send flag.When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent.12120x0R/W1CL1SUB_STATEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_L1SUB_STATE_SETDWC_pcie_wire_cpcie_usp_4x8.csr37542L1Sub State.Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check clkreq_in_n is de-asserted for t_power_off time (only for L1.2, reduces to one cycle for L1.1) - 5h: S_L1_N : L1 substate, turn off txcommonmode circuits (L1.2 only) and rx electrical idle detection circuits - 6h: S_L1_N_EXIT : locally/remotely initiated exit, assert pclkreq, wait for pclkack - 7h: S_L1_N_ABORT : wait for pclkack when aborting an attempt to enter L1_NNote: This register field is sticky.15130x0RLATCHED_NFTSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_LATCHED_NFTS_SETDWC_pcie_wire_cpcie_usp_4x8.csr37557Latched N_FTS.Indicates the value of N_FTS in the received TS Ordered Sets from the Link PartnerNote: This register field is sticky.23160x00RRSVDP_24DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_PM_REG_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr37565Reserved for future use.31240x00RregisterDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L2_REGSD_STATUS_L2_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr376470xBCR0x00fff000DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L2_REGSilicon Debug Status(Layer2).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseTX_TLP_SEQ_NODBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_SETDWC_pcie_wire_cpcie_usp_4x8.csr37585Tx Tlp Sequence Number.Indicates next transmit sequence number for transmit TLP.Note: This register field is sticky.1100x000RRX_ACK_SEQ_NODBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_SETDWC_pcie_wire_cpcie_usp_4x8.csr37599Tx Ack Sequence Number.Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP.Note: This register field is sticky.23120xfffRDLCMSMDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_DLCMSM_SETDWC_pcie_wire_cpcie_usp_4x8.csr37614DLCMSM.Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVENote: This register field is sticky.25240x0RFC_INIT1DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr37627FC_INIT1.Indicates the controller is in FC_INIT1(VC0) state.Note: This register field is sticky.26260x0RFC_INIT2DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_FC_INIT2_SETDWC_pcie_wire_cpcie_usp_4x8.csr37639FC_INIT2.Indicates the controller is in FC_INIT2(VC0) state.Note: This register field is sticky.27270x0RRSVDP_28DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L2_REG_RSVDP_28_SETDWC_pcie_wire_cpcie_usp_4x8.csr37646Reserved for future use.31280x0RregisterDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3FC_REGSD_STATUS_L3FC_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr377710xC0R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REGSilicon Debug Status(Layer3 FC).The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE - CREDIT_SEL_HDFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseCREDIT_SEL_VCDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_SETDWC_pcie_wire_cpcie_usp_4x8.csr37678Credit Select(VC).This field in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 - 0x1: VC1 - 0x2: VC2 - .. - 0x7: VC7Note: This register field is sticky.200x0R/WCREDIT_SEL_CREDIT_TYPEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr37694Credit Select(Credit Type).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Rx - 0x1: TxNote: This register field is sticky.330x0R/WCREDIT_SEL_TLP_TYPEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr37711Credit Select(TLP Type).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Posted - 0x1: Non-Posted - 0x2: CompletionNote: This register field is sticky.540x0R/WCREDIT_SEL_HDDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_SETDWC_pcie_wire_cpcie_usp_4x8.csr37727Credit Select(HeaderData).This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Header Credit - 0x1: Data CreditNote: This register field is sticky.660x0R/WRSVDP_7DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr37735Reserved for future use.770x0RCREDIT_DATA0DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA0_SETDWC_pcie_wire_cpcie_usp_4x8.csr37752Credit Data0.Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed ValueNote: This register field is sticky.1980x000RCREDIT_DATA1DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3FC_REG_CREDIT_DATA1_SETDWC_pcie_wire_cpcie_usp_4x8.csr37770Credit Data1.Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when DLCMSM=0x3(DL_ACTIVE).Note: This register field is sticky.31200x000RregisterDBI_Slave.PF0_RAS_DES_CAP.SD_STATUS_L3_REGSD_STATUS_L3_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr378270xC4R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_SD_STATUS_L3_REGSilicon Debug Status(Layer3).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseMFTLP_POINTERDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_POINTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr37807First Malformed TLP Error Pointer.Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length miss match - 05h: Max payload size - 06h: Message TLP without TC0 - 07h: Invalid TC - 08h: Unexpected route bit in Message TLP - 09h: Unexpected CRS status in Completion TLP - 0Ah: Byte enable - 0Bh: Memory Address 4KB boundary - 0Ch: TLP prefix rules - 0Dh: Translation request rules - 0Eh: Invalid TLP type - 0Fh: Completion rules - 7Fh: Application - Else: ReservedNote: This register field is sticky.600x00RMFTLP_STATUSDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_MFTLP_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr37818Malformed TLP Status.Indicates malformed TLP has occurred.770x0R/W1CRSVDP_8DBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_STATUS_L3_REG_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr37826Reserved for future use.3180x000000RregisterDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL1_REGSD_EQ_CONTROL1_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr379670xD0R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REGSilicon Debug EQ Control 1.This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport registers.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_LANE_SELDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr37855EQ Status Lane Select.Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15Note: This register field is sticky.300x0R/WEQ_RATE_SELDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr37872EQ Status Rate Select.Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed (include ESM data rate) - 0x1: 16.0GT/s Speed (include ESM data rate) - 0x2: 32.0GT/s SpeedNote: This register field is sticky.540x0R/WRSVDP_6DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr37880Reserved for future use.760x0REXT_EQ_TIMEOUTDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EXT_EQ_TIMEOUT_SETDWC_pcie_wire_cpcie_usp_4x8.csr37904Extends EQ Phase2/3 Timeout.This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set, the value of EQ2/3 timeout is extended.EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10: 240ms (x10) - 11: No timeoutEQ Slave(DSP in EQ Phase2/USP in EQ Phase3). - 00: 32ms (default) - 01: 56ms (32ms+24ms) - 10: 248ms (32ms +9*24ms) - 11: No timeoutNote: This register field is sticky.980x0R/WRSVDP_10DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_10_SETDWC_pcie_wire_cpcie_usp_4x8.csr37912Reserved for future use.15100x00REVAL_INTERVAL_TIMEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_SETDWC_pcie_wire_cpcie_usp_4x8.csr37930Eval Interval Time.Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4usThis field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2).Note: This register field is sticky.17160x0R/WRSVDP_18DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr37938Reserved for future use.22180x00RFOM_TARGET_ENABLEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr37950FOM Target Enable.Enables the FOM_TARGET fields.Note: This register field is sticky.23230x0R/WFOM_TARGETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL1_REG_FOM_TARGET_SETDWC_pcie_wire_cpcie_usp_4x8.csr37966FOM Target.Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2).This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit).Note: This register field is sticky.31240x00R/WregisterDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL2_REGSD_EQ_CONTROL2_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr381110xD4R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REGSilicon Debug EQ Control 2.This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_LOCAL_TX_PRE_CURSORDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr37989Force Local Transmitter Pre-cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.500x00R/WFORCE_LOCAL_TX_CURSORDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr38003Force Local Transmitter Cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.1160x00R/WFORCE_LOCAL_TX_POST_CURSORDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr38017Force Local Transmitter Post-Cursor.Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner.Note: This register field is sticky.17120x00R/WFORCE_LOCAL_RX_HINTDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_SETDWC_pcie_wire_cpcie_usp_4x8.csr38034Force Local Receiver Preset Hint.Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.20180x0R/WRSVDP_21DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_21_SETDWC_pcie_wire_cpcie_usp_4x8.csr38042Reserved for future use.23210x0RFORCE_LOCAL_TX_PRESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_SETDWC_pcie_wire_cpcie_usp_4x8.csr38058Force Local Transmitter Preset.Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.Note: This register field is sticky.27240x0R/WFORCE_LOCAL_TX_COEF_ENABLEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr38072Force Local Transmitter Coefficient Enable.Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSORNote: This register field is sticky.28280x0R/WFORCE_LOCAL_RX_HINT_ENABLEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr38087Force Local Receiver Preset Hint Enable.Enables the FORCE_LOCAL_RX_HINT field.If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.29290x0R/WFORCE_LOCAL_TX_PRESET_ENABLEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr38102Force Local Transmitter Preset Enable.Enables the FORCE_LOCAL_TX_PRESET field.If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed, this feature is not available.Note: This register field is sticky.30300x0R/WRSVDP_31DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL2_REG_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr38110Reserved for future use.31310x0RregisterDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_CONTROL3_REGSD_EQ_CONTROL3_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr381950xD8R/W0x00000000DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REGSilicon Debug EQ Control 3.This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseFORCE_REMOTE_TX_PRE_CURSORDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr38133Force Remote Transmitter Pre-Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.500x00R/WFORCE_REMOTE_TX_CURSORDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr38147Force Remote Transmitter Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.1160x00R/WFORCE_REMOTE_TX_POST_CURSORDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr38161Force Remote Transmitter Post-Cursor.Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from local phy in dirchange mode.Note: This register field is sticky.17120x00R/WRSVDP_18DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr38169Reserved for future use.27180x000RFORCE_REMOTE_TX_COEF_ENABLEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr38186Force Remote Transmitter Coefficient Enable.Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSORThis function can only be used when GEN3_EQ_FB_MODE = 0000b(Direction Change)Note: This register field is sticky.28280x0R/WRSVDP_29DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_CONTROL3_REG_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr38194Reserved for future use.31290x0RregisterDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS1_REGSD_EQ_STATUS1_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr383390xE0R0x00000000DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REGSilicon Debug EQ Status 1.This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.The following fields are available when Equalization finished unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_VIOLATION - EQ_REJECT_EVENTFor more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_SEQUENCEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_SEQUENCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr38225EQ Sequence.Indicates that the controller is starting the equalization sequence.Note: This register field is sticky.000x0REQ_CONVERGENCE_INFODBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_SETDWC_pcie_wire_cpcie_usp_4x8.csr38244EQ Convergence Info.Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: ReservedThis bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.210x0RRSVDP_3DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr38251Reserved for future use.330x0REQ_RULEA_VIOLATIONDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_SETDWC_pcie_wire_cpcie_usp_4x8.csr38272EQ Rule A Violation.Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to the rules a) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.440x0REQ_RULEB_VIOLATIONDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_SETDWC_pcie_wire_cpcie_usp_4x8.csr38293EQ Rule B Violation.Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to the rules b) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.550x0REQ_RULEC_VIOLATIONDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_SETDWC_pcie_wire_cpcie_usp_4x8.csr38314EQ Rule C Violation.Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to the rules c) from section "Rules for Transmitter Coefficents" in the PCI Express Base Specification.This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.660x0REQ_REJECT_EVENTDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_SETDWC_pcie_wire_cpcie_usp_4x8.csr38331EQ Reject Event.Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2).This bit is automatically cleared when the controller starts EQ Master phase again.Note: This register field is sticky.770x0RRSVDP_8DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS1_REG_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr38338Reserved for future use.3180x000000RregisterDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS2_REGSD_EQ_STATUS2_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr384270xE4R0x00000000DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REGSilicon Debug EQ Status 2.This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_LOCAL_PRE_CURSORDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr38364EQ Local Pre-Cursor.Indicates Local pre cursor coefficient value.Note: This register field is sticky.500x00REQ_LOCAL_CURSORDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr38377EQ Local Cursor.Indicates Local cursor coefficient value.Note: This register field is sticky.1160x00REQ_LOCAL_POST_CURSORDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr38390EQ Local Post-Cursor.Indicates Local post cursor coefficient value.Note: This register field is sticky.17120x00REQ_LOCAL_RX_HINTDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_SETDWC_pcie_wire_cpcie_usp_4x8.csr38406EQ Local Receiver Preset Hint.Indicates Local Receiver Preset Hint value.If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed, this feature is not available.Note: This register field is sticky.20180x0RRSVDP_21DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_RSVDP_21_SETDWC_pcie_wire_cpcie_usp_4x8.csr38413Reserved for future use.23210x0REQ_LOCAL_FOM_VALUEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr38426EQ Local Figure of Merit.Indicates Local maximum Figure of Merit value.Note: This register field is sticky.31240x00RregisterDBI_Slave.PF0_RAS_DES_CAP.SD_EQ_STATUS3_REGSD_EQ_STATUS3_REGDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_OFFSETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr385120xE8R0x00000000DBI_Slave_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REGSilicon Debug EQ Status 3.This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1).For more details, see the RAS DES section in the Core Operations chapter of the Databook.falsefalsefalsefalseEQ_REMOTE_PRE_CURSORDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr38452EQ Remote Pre-Cursor.Indicates Remote pre cursor coefficient value.Note: This register field is sticky.500x00REQ_REMOTE_CURSORDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr38465EQ Remote Cursor.Indicates Remote cursor coefficient value.Note: This register field is sticky.1160x00REQ_REMOTE_POST_CURSORDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr38478EQ Remote Post-Cursor.Indicates Remote post cursor coefficient value.Note: This register field is sticky.17120x00REQ_REMOTE_LFDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_SETDWC_pcie_wire_cpcie_usp_4x8.csr38491EQ Remote LF.Indicates Remote LF value.Note: This register field is sticky.23180x00REQ_REMOTE_FSDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_SETDWC_pcie_wire_cpcie_usp_4x8.csr38504EQ Remote FS.Indicates Remote FS value.Note: This register field is sticky.29240x00RRSVDP_30DBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_WIDTHDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_MSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_LSBDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_RANGEDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_RESETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_FIELD_MASKDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_GETDBI_SLAVE_PF0_RAS_DES_CAP_SD_EQ_STATUS3_REG_RSVDP_30_SETDWC_pcie_wire_cpcie_usp_4x8.csr38511Reserved for future use.31300x0RgroupDBI_Slave.PF0_VSECRAS_CAPPF0_VSECRAS_CAPDBI_SLAVE_PF0_VSECRAS_CAP_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr395660x3C4R/WDBI_Slave_PF0_VSECRAS_CAPPF RAS Datapath Protection Capability Structure (VSEC)registerDBI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_EXT_CAP_HDR_OFFRASDP_EXT_CAP_HDR_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr385730x0R0x3fc1000bDBI_Slave_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFFPCIe Extended capability ID, Capability version and Next capability offset.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseIDDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr38540PCI Express Extended Capability ID.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x000bRCAPDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_CAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr38556Capability Version.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RNEXT_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr38572Next Capability Offset.For a description of this standard PCIe register, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x3fcRregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_VENDOR_SPECIFIC_HDR_OFFRASDP_VENDOR_SPECIFIC_HDR_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr386160x4R0x03810001DBI_Slave_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFFVendor Specific Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVSEC_IDDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr38591VSEC ID.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.1500x0001RVSEC_REVDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_SETDWC_pcie_wire_cpcie_usp_4x8.csr38603VSEC Rev.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.19160x1RVSEC_LENGTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr38615VSEC Length.For a description of this standard PCIe register, see the PCI Express Specification.Note: This register field is sticky.31200x038RregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_PROT_CTRL_OFFRASDP_ERROR_PROT_CTRL_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr38822ECC error correction control0x8R/W0x00000000DBI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFFECC error correction control. Allows you to disable ECC error correction for RAMs and datapath.When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock (core_clk), you must not write this register while operations are in progress in the AXI master / slave interface.falsefalsefalsefalseERROR_PROT_DISABLE_TXDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_SETDWC_pcie_wire_cpcie_usp_4x8.csr38640Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.Note: This register field is sticky.000x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_MASTERDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr38651Error correction disable for AXI bridge master completion buffer.Note: This register field is sticky.110x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUNDDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_SETDWC_pcie_wire_cpcie_usp_4x8.csr38662Error correction disable for AXI bridge outbound request path.Note: This register field is sticky.220x0R/WERROR_PROT_DISABLE_DMA_WRITEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_SETDWC_pcie_wire_cpcie_usp_4x8.csr38672Error correction disable for DMA write engine.Note: This register field is sticky.330x0R/WERROR_PROT_DISABLE_LAYER2_TXDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_SETDWC_pcie_wire_cpcie_usp_4x8.csr38682Error correction disable for layer 2 Tx path.Note: This register field is sticky.440x0R/WERROR_PROT_DISABLE_LAYER3_TXDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_SETDWC_pcie_wire_cpcie_usp_4x8.csr38692Error correction disable for layer 3 Tx path.Note: This register field is sticky.550x0R/WERROR_PROT_DISABLE_ADM_TXDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_SETDWC_pcie_wire_cpcie_usp_4x8.csr38702Error correction disable for Adm Tx path.Note: This register field is sticky.660x0R/WERROR_PROT_DISABLE_CXS_TXDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_TX_SETDWC_pcie_wire_cpcie_usp_4x8.csr38712Error correction disable for CXS Rx path (PCIe Tx path).Note: This register field is sticky.770x0R/WERROR_PROT_DISABLE_DTIM_TXDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DTIM_TX_SETDWC_pcie_wire_cpcie_usp_4x8.csr38722Error correction disable for DTIM Tx path.Note: This register field is sticky.880x0R/WRSVDP_9DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr38730Reserved for future use.1590x00RERROR_PROT_DISABLE_RXDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_SETDWC_pcie_wire_cpcie_usp_4x8.csr38740Global error correction disable for all Rx layers.Note: This register field is sticky.16160x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETIONDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_SETDWC_pcie_wire_cpcie_usp_4x8.csr38752Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.Note: This register field is sticky.17170x0R/WERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUESTDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_SETDWC_pcie_wire_cpcie_usp_4x8.csr38763Error correction disable for AXI bridge inbound request path.Note: This register field is sticky.18180x0R/WERROR_PROT_DISABLE_DMA_READDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_SETDWC_pcie_wire_cpcie_usp_4x8.csr38773Error correction disable for DMA read engine.Note: This register field is sticky.19190x0R/WERROR_PROT_DISABLE_LAYER2_RXDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_SETDWC_pcie_wire_cpcie_usp_4x8.csr38783Error correction disable for layer 2 Rx path.Note: This register field is sticky.20200x0R/WERROR_PROT_DISABLE_LAYER3_RXDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_SETDWC_pcie_wire_cpcie_usp_4x8.csr38793Error correction disable for layer 3 Rx path.Note: This register field is sticky.21210x0R/WERROR_PROT_DISABLE_ADM_RXDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_SETDWC_pcie_wire_cpcie_usp_4x8.csr38803Error correction disable for ADM Rx path.Note: This register field is sticky.22220x0R/WERROR_PROT_DISABLE_CXS_RXDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_CXS_RX_SETDWC_pcie_wire_cpcie_usp_4x8.csr38813Error correction disable for CXS Tx path (PCIe Rx path).Note: This register field is sticky.23230x0R/WRSVDP_24DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr38821Reserved for future use.31240x00RregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNTER_CTRL_OFFRASDP_CORR_COUNTER_CTRL_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr389090xCR/W0x00000010DBI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFFCorrected error (1-bit ECC) counter selection and control.This is a viewport control register.Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_CORR_COUNT_REPORT_OFF viewport data register.falsefalsefalsefalseCORR_CLEAR_COUNTERSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_SETDWC_pcie_wire_cpcie_usp_4x8.csr38839Clear all correctable error counters.000x0WRSVDP_1DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr38847Reserved for future use.310x0RCORR_EN_COUNTERSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_SETDWC_pcie_wire_cpcie_usp_4x8.csr38859Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozenThe counters are enabled by default.440x1R/WRSVDP_5DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr38867Reserved for future use.1950x0000RCORR_COUNTER_SELECTION_REGIONDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_SETDWC_pcie_wire_cpcie_usp_4x8.csr38893Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0R/WCORR_COUNTER_SELECTIONDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_SETDWC_pcie_wire_cpcie_usp_4x8.csr38908Counter selection.This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00R/WregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_COUNT_REPORT_OFFRASDP_CORR_COUNT_REPORT_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr389710x10R0x00000000DBI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFFCorrected error (1-bit ECC) counter data.This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register.falsefalsefalsefalseCORR_COUNTERDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr38925Current corrected error count for the selected counter.700x00RRSVDP_8DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr38932Reserved for future use.1980x000RCORR_COUNTER_SELECTED_REGIONDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_SETDWC_pcie_wire_cpcie_usp_4x8.csr38959Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0RCORR_COUNTER_SELECTEDDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr38970Counter selection.Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register.31240x00RregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNTER_CTRL_OFFRASDP_UNCORR_COUNTER_CTRL_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr390620x14R/W0x00000010DBI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFFUncorrected error (2-bit ECC and parity) counter selection and control.This is a viewport control register.Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_UNCORR_COUNT_REPORT_OFF viewport data register.falsefalsefalsefalseUNCORR_CLEAR_COUNTERSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_SETDWC_pcie_wire_cpcie_usp_4x8.csr38991Clear uncorrectable errors counters.When asserted causes all counters tracking the uncorrectable errors to be cleared.000x0WRSVDP_1DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr38999Reserved for future use.310x0RUNCORR_EN_COUNTERSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_SETDWC_pcie_wire_cpcie_usp_4x8.csr39011Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozenThe counters are enabled by default.440x1R/WRSVDP_5DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr39019Reserved for future use.1950x0000RUNCORR_COUNTER_SELECTION_REGIONDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_SETDWC_pcie_wire_cpcie_usp_4x8.csr39045Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0R/WUNCORR_COUNTER_SELECTIONDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_SETDWC_pcie_wire_cpcie_usp_4x8.csr39061Counter selection.This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00R/WregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_COUNT_REPORT_OFFRASDP_UNCORR_COUNT_REPORT_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr391250x18R0x00000000DBI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFFUncorrected error (2-bit ECC and parity) counter data.This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF register.falsefalsefalsefalseUNCORR_COUNTERDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SETDWC_pcie_wire_cpcie_usp_4x8.csr39079Current uncorrected error count for the selected counter700x00RRSVDP_8DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr39086Reserved for future use.1980x000RUNCORR_COUNTER_SELECTED_REGIONDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_SETDWC_pcie_wire_cpcie_usp_4x8.csr39113Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200x0RUNCORR_COUNTER_SELECTEDDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr39124Counter selection.Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register.31240x00RregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_INJ_CTRL_OFFRASDP_ERROR_INJ_CTRL_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr39205Error injection control0x1CR/W0x00000000DBI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFFError injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occursfalsefalsefalsefalseERROR_INJ_ENDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr39143Error injection global enable.When set enables the error insertion logic.000x0R/WRSVDP_1DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr39151Reserved for future use.310x0RERROR_INJ_TYPEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr39162Error injection type: - 0: none - 1: 1-bit - 2: 2-bit540x0R/WRSVDP_6DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr39170Reserved for future use.760x0RERROR_INJ_COUNTDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr39183Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected1580x00R/WERROR_INJ_LOCDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_SETDWC_pcie_wire_cpcie_usp_4x8.csr39196Error injection location.Selects where error injection takes place.You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf23160x00R/WRSVDP_24DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr39204Reserved for future use.31240x00RregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_CORR_ERROR_LOCATION_OFFRASDP_CORR_ERROR_LOCATION_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr39312Corrected errors locations.0x20R0x00d000d0DBI_Slave_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFFCorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr39220Reserved for future use.300x0RREG_FIRST_CORR_ERRORDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr39247Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved740xdRLOC_FIRST_CORR_ERRORDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr39262Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf1580x00RRSVDP_16DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr39269Reserved for future use.19160x0RREG_LAST_CORR_ERRORDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr39296Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200xdRLOC_LAST_CORR_ERRORDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr39311Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00RregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_UNCORR_ERROR_LOCATION_OFFRASDP_UNCORR_ERROR_LOCATION_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr39419Uncorrected errors locations.0x24R0x00d000d0DBI_Slave_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFFUncorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr39327Reserved for future use.300x0RREG_FIRST_UNCORR_ERRORDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr39354Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved740xdRLOC_FIRST_UNCORR_ERRORDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr39369Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf1580x00RRSVDP_16DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr39376Reserved for future use.19160x0RREG_LAST_UNCORR_ERRORDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr39403Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Region select for CXS Tx/Rx path - 0xd: Region select for DTIM Tx/Rx path - 0xe: Reserved - 0xf: Reserved23200xdRLOC_LAST_UNCORR_ERRORDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr39418Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR.You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf31240x00RregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_EN_OFFRASDP_ERROR_MODE_EN_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr39463RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error.0x28R/W0x00000001DBI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFFRASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be correct; you must discard them.For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_MODE_ENDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr39443Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error.Note: This register field is sticky.000x1R/WAUTO_LINK_DOWN_ENDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr39454Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode.Note: This register field is sticky.110x0R/WRSVDP_2DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr39462Reserved for future use.3120x00000000RregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_ERROR_MODE_CLEAR_OFFRASDP_ERROR_MODE_CLEAR_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr39491Exit RASDP error mode.0x2CR/W0x00000000DBI_Slave_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFFExit RASDP error mode. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseERROR_MODE_CLEARDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_SETDWC_pcie_wire_cpcie_usp_4x8.csr39482Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs.000x0WRSVDP_1DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr39490Reserved for future use.3110x00000000RregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_CORR_ERROR_OFFRASDP_RAM_ADDR_CORR_ERROR_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr39528RAM Address where a corrected error (1-bit ECC) has been detected.0x30R0x00000000DBI_Slave_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFFRAM Address where a corrected error (1-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRAM_ADDR_CORR_ERRORDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr39510RAM Address where a corrected error (1-bit ECC) has been detected.2600x0000000RRSVDP_27DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr39517Reserved for future use.27270x0RRAM_INDEX_CORR_ERRORDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr39527RAM index where a corrected error (1-bit ECC) has been detected.31280x0RregisterDBI_Slave.PF0_VSECRAS_CAP.RASDP_RAM_ADDR_UNCORR_ERROR_OFFRASDP_RAM_ADDR_UNCORR_ERROR_OFFDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_OFFSETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr39565RAM Address where an uncorrected error (2-bit ECC) has been detected.0x34R0x00000000DBI_Slave_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFFRAM Address where an uncorrected error (2-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.falsefalsefalsefalseRAM_ADDR_UNCORR_ERRORDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr39547RAM Address where an uncorrected error (2-bit ECC) has been detected.2600x0000000RRSVDP_27DBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr39554Reserved for future use.27270x0RRAM_INDEX_UNCORR_ERRORDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_WIDTHDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_MSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_LSBDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_RANGEDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_RESETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_FIELD_MASKDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_GETDBI_SLAVE_PF0_VSECRAS_CAP_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_SETDWC_pcie_wire_cpcie_usp_4x8.csr39564RAM index where an uncorrected error (2-bit ECC) has been detected.31280x0RgroupDBI_Slave.PF0_DLINK_CAPPF0_DLINK_CAPDBI_SLAVE_PF0_DLINK_CAP_ADDRESSDBI_SLAVE_PF0_DLINK_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_DLINK_CAP_OFFSETDBI_SLAVE_PF0_DLINK_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr397460x3FCRDBI_Slave_PF0_DLINK_CAPPF DLINK Capability StructureregisterDBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFregisterDBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFregisterDBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFregisterDBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_EXT_HDR_OFFDATA_LINK_FEATURE_EXT_HDR_OFFDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_ADDRESSDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_OFFSETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr39640This register provides capbility ID, capability version and next offset value.0x0R0x40810025DBI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFFData Link Feature Extended Capability Header.This register provides capbility ID, capability version and next offset value.falsefalsefalsefalseDLINK_EXT_CAP_IDDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_WIDTHDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_MSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_LSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_RANGEDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_RESETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_GETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_EXT_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr39596Capability ID.This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability.Extended Capability ID for Data Link Feature is 0025h.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0025RDLINK_CAP_VERSIONDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_WIDTHDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_MSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_LSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_RANGEDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_RESETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_FIELD_MASKDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_GETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr39613Capability Version.This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.This field is depends on version of the specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RDLINK_NEXT_OFFSETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_MSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_LSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_RESETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_GETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_EXT_HDR_OFF_DLINK_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr39639Next Capability Offset.This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities.For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.The bottom 2 bits of this offset are Reserved and must be implemented as 00b although software must mask them to allow for future uses of these bits.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x408RregisterDBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_CAP_OFFDATA_LINK_FEATURE_CAP_OFFDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_ADDRESSDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_OFFSETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr39701This register provides description about extended feature.0x4R0x80000001DBI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFFData Link Feature Capabilities.This register provides description about extended feature.falsefalsefalsefalseSCALED_FLOW_CNTL_SUPPORTEDDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_WIDTHDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_MSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_LSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_RANGEDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_RESETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_FIELD_MASKDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_GETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_SCALED_FLOW_CNTL_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr39664Local Scaled Flow Control Supported.Bit 0 – Local Scaled Flow Control Supported. Bit 22:1 – RsvdP.Bits associated with features that this Port is capable of supporting are HwInit, defaulting to 1b.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 000x1RFUTURE_FEATURE_SUPPORTEDDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_WIDTHDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_MSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_LSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_RANGEDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_RESETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_FIELD_MASKDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_GETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_FUTURE_FEATURE_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr39678Local Future Data Link Feature Supported.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.2210x000000RRSVDP_23DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_WIDTHDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_MSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_LSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_RANGEDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_RESETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_GETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr39685Reserved for future use.30230x00RDL_FEATURE_EXCHANGE_ENDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_WIDTHDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_MSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_LSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_RANGEDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_RESETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_FIELD_MASKDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_GETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_CAP_OFF_DL_FEATURE_EXCHANGE_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr39700Data Link Feature Exchange Enable.If Set, this bit indicates that this Port will enter the DL_Feature negotiation state. Default is 1b.Note: The access attributes of this field are as follows: - Wire: HWINIT - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) 31310x1RregisterDBI_Slave.PF0_DLINK_CAP.DATA_LINK_FEATURE_STATUS_OFFDATA_LINK_FEATURE_STATUS_OFFDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_OFFSETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr39745This Registor privides status of the capability of data link feature.0x8R0x00000000DBI_Slave_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFFData Link Feature Status Register.This Registor privides status of the capability of data link feature.falsefalsefalsefalseREMOTE_DATA_LINK_FEATURE_SUPPORTEDDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_WIDTHDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_MSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_LSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_RANGEDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_RESETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_FIELD_MASKDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_GETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_REMOTE_DATA_LINK_FEATURE_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr39722Remote Data Link Feature SupportedFeatures Currently defined are: Bit 0 - Remote Scaled Flow Control Supported.Other Bits are undefined. Default value is 00 0000h.2200x000000RRSVDP_23DBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_WIDTHDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_MSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_LSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_RANGEDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_RESETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_GETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr39729Reserved for future use.30230x00RDATA_LINK_FEATURE_STATUS_VALIDDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_WIDTHDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_MSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_LSBDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_RANGEDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_RESETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_FIELD_MASKDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_GETDBI_SLAVE_PF0_DLINK_CAP_DATA_LINK_FEATURE_STATUS_OFF_DATA_LINK_FEATURE_STATUS_VALID_SETDWC_pcie_wire_cpcie_usp_4x8.csr39744Remote Data Link Feature Supported Valid.This bit indicates that the Port has received a Data Link Feature DLLP in state DL_Feature (see Section 3.2.1) and that the Remote Data Link Feature Supported and Remote Data Link Feature Ack fields arefield is meaningful. This bit is Cleared on entry to state DL_Inactive.Default is 0b.31310x0RgroupDBI_Slave.PF0_RESBAR_CAPPF0_RESBAR_CAPDBI_SLAVE_PF0_RESBAR_CAP_ADDRESSDBI_SLAVE_PF0_RESBAR_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_RESBAR_CAP_OFFSETDBI_SLAVE_PF0_RESBAR_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr406480x408R/WDBI_Slave_PF0_RESBAR_CAPResizable BAR Capability StructureregisterDBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REGregisterDBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REGregisterDBI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REGregisterDBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_HDR_REGRESBAR_CAP_HDR_REGDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_ADDRESSDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_OFFSETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr398050x0R0x44810015DBI_Slave_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REGResizable BAR Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRESBAR_EXT_CAP_IDDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr39772Resizable BAR Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0015RRESBAR_CAP_VERSIONDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr39788Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RRESBAR_CAP_NEXT_OFFSETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr39804Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x448RregisterDBI_Slave.PF0_RESBAR_CAP.RESBAR_CAP_REG_0_REGRESBAR_CAP_REG_0_REGDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_ADDRESSDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_OFFSETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr402950x4R0x00000010DBI_Slave_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REGResizable BAR0 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr39818Reserved for future use.300x0RRESBAR_CAP_REG_0_1MBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr39835Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1RRESBAR_CAP_REG_0_2MBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr39852Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0RRESBAR_CAP_REG_0_4MBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr39869Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0RRESBAR_CAP_REG_0_8MBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr39886Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0RRESBAR_CAP_REG_0_16MBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr39903Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RRESBAR_CAP_REG_0_32MBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr39920Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RRESBAR_CAP_REG_0_64MBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr39937Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RRESBAR_CAP_REG_0_128MBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr39954Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0RRESBAR_CAP_REG_0_256MBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr39971Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0RRESBAR_CAP_REG_0_512MBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr39988Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0RRESBAR_CAP_REG_0_1GBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40005Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0RRESBAR_CAP_REG_0_2GBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40022Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0RRESBAR_CAP_REG_0_4GBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40039Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RRESBAR_CAP_REG_0_8GBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40056Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RRESBAR_CAP_REG_0_16GBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40073Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RRESBAR_CAP_REG_0_32GBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40090Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RRESBAR_CAP_REG_0_64GBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40107Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RRESBAR_CAP_REG_0_128GBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40124Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RRESBAR_CAP_REG_0_256GBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40141Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RRESBAR_CAP_REG_0_512GBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40158Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RRESBAR_CAP_REG_0_1TBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40175Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RRESBAR_CAP_REG_0_2TBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40192Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RRESBAR_CAP_REG_0_4TBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40209Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RRESBAR_CAP_REG_0_8TBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40226Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RRESBAR_CAP_REG_0_16TBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40243Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RRESBAR_CAP_REG_0_32TBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40260Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RRESBAR_CAP_REG_0_64TBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40277Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RRESBAR_CAP_REG_0_128TBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40294Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RregisterDBI_Slave.PF0_RESBAR_CAP.RESBAR_CTRL_REG_0_REGRESBAR_CTRL_REG_0_REGDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_ADDRESSDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_BYTE_ADDRESSDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_OFFSETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr406470x8R/W0x00000020DBI_Slave_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REGResizable BAR0 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRESBAR_CTRL_REG_IDX_0DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr40314BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr40322Reserved for future use.430x0RRESBAR_CTRL_REG_NUM_BARSDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_wire_cpcie_usp_4x8.csr40336Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x1RRESBAR_CTRL_REG_BAR_SIZEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr40350BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14DBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr40358Reserved for future use.15140x0RRESBAR_CTRL_REG_0_256TBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40376Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RRESBAR_CTRL_REG_0_512TBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40394Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RRESBAR_CTRL_REG_0_1PBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40412Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RRESBAR_CTRL_REG_0_2PBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40430Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RRESBAR_CTRL_REG_0_4PBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40448Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RRESBAR_CTRL_REG_0_8PBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40466Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RRESBAR_CTRL_REG_0_16PBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_16PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40484Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RRESBAR_CTRL_REG_0_32PBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_32PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40502Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RRESBAR_CTRL_REG_0_64PBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_64PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40520Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RRESBAR_CTRL_REG_0_128PBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_128PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40538Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RRESBAR_CTRL_REG_0_256PBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_256PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40556Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RRESBAR_CTRL_REG_0_512PBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_512PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40574Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RRESBAR_CTRL_REG_0_1EBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_1EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40592Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RRESBAR_CTRL_REG_0_2EBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_2EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40610Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RRESBAR_CTRL_REG_0_4EBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_4EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40628Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RRESBAR_CTRL_REG_0_8EBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_WIDTHDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_MSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_LSBDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_RANGEDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_RESETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_FIELD_MASKDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_GETDBI_SLAVE_PF0_RESBAR_CAP_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_0_8EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40646Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RgroupDBI_Slave.PF0_VF_RESBAR_CAPPF0_VF_RESBAR_CAPDBI_SLAVE_PF0_VF_RESBAR_CAP_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_BYTE_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_OFFSETDBI_SLAVE_PF0_VF_RESBAR_CAP_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr432340x448R/WDBI_Slave_PF0_VF_RESBAR_CAPVF Resizable BAR Capability StructureregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REGregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REGregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REGregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REGregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REGregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REGregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REGregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_HDR_REGVF_RESBAR_CAP_HDR_REGDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_BYTE_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_OFFSETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr407070x0R0x00010024DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REGResizable BAR Capability Header.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_EXT_CAP_IDDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_EXT_CAP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr40674Resizable BAR Extended Capability ID.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.1500x0024RVF_RESBAR_CAP_VERSIONDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_VERSION_SETDWC_pcie_wire_cpcie_usp_4x8.csr40690Capability Version.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19160x1RVF_RESBAR_CAP_NEXT_OFFSETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_HDR_REG_VF_RESBAR_CAP_NEXT_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr40706Next Capability Offset.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31200x000RregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_0_REGVF_RESBAR_CAP_REG_0_REGDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_BYTE_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_OFFSETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr411970x4R0x00000010DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REGResizable BAR0 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr40720Reserved for future use.300x0RVF_RESBAR_CAP_REG_0_1MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40737Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1RVF_RESBAR_CAP_REG_0_2MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40754Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0RVF_RESBAR_CAP_REG_0_4MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40771Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0RVF_RESBAR_CAP_REG_0_8MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40788Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0RVF_RESBAR_CAP_REG_0_16MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40805Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RVF_RESBAR_CAP_REG_0_32MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40822Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RVF_RESBAR_CAP_REG_0_64MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40839Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RVF_RESBAR_CAP_REG_0_128MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40856Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0RVF_RESBAR_CAP_REG_0_256MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40873Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0RVF_RESBAR_CAP_REG_0_512MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40890Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0RVF_RESBAR_CAP_REG_0_1GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40907Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0RVF_RESBAR_CAP_REG_0_2GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40924Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0RVF_RESBAR_CAP_REG_0_4GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40941Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RVF_RESBAR_CAP_REG_0_8GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40958Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RVF_RESBAR_CAP_REG_0_16GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40975Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RVF_RESBAR_CAP_REG_0_32GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr40992Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RVF_RESBAR_CAP_REG_0_64GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41009Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RVF_RESBAR_CAP_REG_0_128GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41026Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RVF_RESBAR_CAP_REG_0_256GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_256GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41043Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RVF_RESBAR_CAP_REG_0_512GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_512GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41060Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RVF_RESBAR_CAP_REG_0_1TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_1TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41077Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RVF_RESBAR_CAP_REG_0_2TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_2TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41094Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RVF_RESBAR_CAP_REG_0_4TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_4TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41111Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RVF_RESBAR_CAP_REG_0_8TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_8TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41128Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RVF_RESBAR_CAP_REG_0_16TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_16TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41145Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RVF_RESBAR_CAP_REG_0_32TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_32TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41162Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RVF_RESBAR_CAP_REG_0_64TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_64TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41179Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RVF_RESBAR_CAP_REG_0_128TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_0_REG_VF_RESBAR_CAP_REG_0_128TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41196Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_0_REGVF_RESBAR_CTRL_REG_0_REGDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_BYTE_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_OFFSETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr415490x8R/W0x00000060DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REGResizable BAR0 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_CTRL_REG_IDX_0DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_IDX_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr41216BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr41224Reserved for future use.430x0RVF_RESBAR_CTRL_REG_NUM_BARSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_wire_cpcie_usp_4x8.csr41238Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x3RVF_RESBAR_CTRL_REG_BAR_SIZEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr41252BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr41260Reserved for future use.15140x0RVF_RESBAR_CTRL_REG_0_256TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41278Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RVF_RESBAR_CTRL_REG_0_512TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41296Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RVF_RESBAR_CTRL_REG_0_1PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41314Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RVF_RESBAR_CTRL_REG_0_2PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41332Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RVF_RESBAR_CTRL_REG_0_4PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41350Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RVF_RESBAR_CTRL_REG_0_8PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41368Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RVF_RESBAR_CTRL_REG_0_16PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_16PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41386Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RVF_RESBAR_CTRL_REG_0_32PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_32PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41404Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RVF_RESBAR_CTRL_REG_0_64PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_64PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41422Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RVF_RESBAR_CTRL_REG_0_128PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_128PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41440Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RVF_RESBAR_CTRL_REG_0_256PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_256PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41458Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RVF_RESBAR_CTRL_REG_0_512PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_512PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41476Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RVF_RESBAR_CTRL_REG_0_1EBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_1EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41494Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RVF_RESBAR_CTRL_REG_0_2EBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_2EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41512Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RVF_RESBAR_CTRL_REG_0_4EBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_4EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41530Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RVF_RESBAR_CTRL_REG_0_8EBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_0_REG_VF_RESBAR_CTRL_REG_0_8EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41548Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_1_REGVF_RESBAR_CAP_REG_1_REGDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_BYTE_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_OFFSETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr420390xCR0x00000010DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REGResizable BAR1 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr41562Reserved for future use.300x0RVF_RESBAR_CAP_REG_1_1MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41579Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1RVF_RESBAR_CAP_REG_1_2MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41596Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0RVF_RESBAR_CAP_REG_1_4MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41613Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0RVF_RESBAR_CAP_REG_1_8MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41630Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0RVF_RESBAR_CAP_REG_1_16MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41647Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RVF_RESBAR_CAP_REG_1_32MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41664Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RVF_RESBAR_CAP_REG_1_64MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41681Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RVF_RESBAR_CAP_REG_1_128MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41698Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0RVF_RESBAR_CAP_REG_1_256MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41715Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0RVF_RESBAR_CAP_REG_1_512MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41732Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0RVF_RESBAR_CAP_REG_1_1GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41749Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0RVF_RESBAR_CAP_REG_1_2GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41766Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0RVF_RESBAR_CAP_REG_1_4GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41783Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RVF_RESBAR_CAP_REG_1_8GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41800Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RVF_RESBAR_CAP_REG_1_16GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41817Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RVF_RESBAR_CAP_REG_1_32GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41834Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RVF_RESBAR_CAP_REG_1_64GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41851Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RVF_RESBAR_CAP_REG_1_128GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41868Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RVF_RESBAR_CAP_REG_1_256GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_256GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41885Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RVF_RESBAR_CAP_REG_1_512GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_512GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41902Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RVF_RESBAR_CAP_REG_1_1TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_1TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41919Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RVF_RESBAR_CAP_REG_1_2TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_2TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41936Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RVF_RESBAR_CAP_REG_1_4TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_4TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41953Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RVF_RESBAR_CAP_REG_1_8TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_8TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41970Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RVF_RESBAR_CAP_REG_1_16TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_16TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr41987Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RVF_RESBAR_CAP_REG_1_32TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_32TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42004Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RVF_RESBAR_CAP_REG_1_64TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_64TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42021Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RVF_RESBAR_CAP_REG_1_128TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_1_REG_VF_RESBAR_CAP_REG_1_128TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42038Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_1_REGVF_RESBAR_CTRL_REG_1_REGDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_BYTE_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_OFFSETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr423910x10R/W0x00000000DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REGResizable BAR1 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_CTRL_REG_IDX_1DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_IDX_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr42058BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr42066Reserved for future use.430x0RVF_RESBAR_CTRL_REG_NUM_BARSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_wire_cpcie_usp_4x8.csr42080Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x0RVF_RESBAR_CTRL_REG_BAR_SIZEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr42094BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr42102Reserved for future use.15140x0RVF_RESBAR_CTRL_REG_1_256TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42120Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RVF_RESBAR_CTRL_REG_1_512TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42138Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RVF_RESBAR_CTRL_REG_1_1PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42156Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RVF_RESBAR_CTRL_REG_1_2PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42174Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RVF_RESBAR_CTRL_REG_1_4PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42192Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RVF_RESBAR_CTRL_REG_1_8PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42210Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RVF_RESBAR_CTRL_REG_1_16PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_16PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42228Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RVF_RESBAR_CTRL_REG_1_32PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_32PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42246Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RVF_RESBAR_CTRL_REG_1_64PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_64PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42264Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RVF_RESBAR_CTRL_REG_1_128PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_128PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42282Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RVF_RESBAR_CTRL_REG_1_256PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_256PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42300Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RVF_RESBAR_CTRL_REG_1_512PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_512PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42318Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RVF_RESBAR_CTRL_REG_1_1EBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_1EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42336Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RVF_RESBAR_CTRL_REG_1_2EBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_2EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42354Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RVF_RESBAR_CTRL_REG_1_4EBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_4EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42372Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RVF_RESBAR_CTRL_REG_1_8EBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_1_REG_VF_RESBAR_CTRL_REG_1_8EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42390Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CAP_REG_2_REGVF_RESBAR_CAP_REG_2_REGDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_OFFSETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr428810x14R0x00000010DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REGResizable BAR2 Capability Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr42404Reserved for future use.300x0RVF_RESBAR_CAP_REG_2_1MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42421Up to 1MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.440x1RVF_RESBAR_CAP_REG_2_2MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42438Up to 2MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.550x0RVF_RESBAR_CAP_REG_2_4MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42455Up to 4MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.660x0RVF_RESBAR_CAP_REG_2_8MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42472Up to 8MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.770x0RVF_RESBAR_CAP_REG_2_16MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42489Up to 16MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.880x0RVF_RESBAR_CAP_REG_2_32MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42506Up to 32MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.990x0RVF_RESBAR_CAP_REG_2_64MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42523Up to 64MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.10100x0RVF_RESBAR_CAP_REG_2_128MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42540Up to 128MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.11110x0RVF_RESBAR_CAP_REG_2_256MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42557Up to 256MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.12120x0RVF_RESBAR_CAP_REG_2_512MBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512MB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42574Up to 512MB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.13130x0RVF_RESBAR_CAP_REG_2_1GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42591Up to 1GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.14140x0RVF_RESBAR_CAP_REG_2_2GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42608Up to 2GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.15150x0RVF_RESBAR_CAP_REG_2_4GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42625Up to 4GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RVF_RESBAR_CAP_REG_2_8GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42642Up to 8GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RVF_RESBAR_CAP_REG_2_16GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42659Up to 16GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RVF_RESBAR_CAP_REG_2_32GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42676Up to 32GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RVF_RESBAR_CAP_REG_2_64GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42693Up to 64GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RVF_RESBAR_CAP_REG_2_128GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42710Up to 128GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RVF_RESBAR_CAP_REG_2_256GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_256GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42727Up to 256GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RVF_RESBAR_CAP_REG_2_512GBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_512GB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42744Up to 512GB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RVF_RESBAR_CAP_REG_2_1TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_1TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42761Up to 1TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RVF_RESBAR_CAP_REG_2_2TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_2TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42778Up to 2TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RVF_RESBAR_CAP_REG_2_4TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_4TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42795Up to 4TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RVF_RESBAR_CAP_REG_2_8TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_8TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42812Up to 8TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RVF_RESBAR_CAP_REG_2_16TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_16TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42829Up to 16TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RVF_RESBAR_CAP_REG_2_32TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_32TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42846Up to 32TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RVF_RESBAR_CAP_REG_2_64TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_64TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42863Up to 64TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RVF_RESBAR_CAP_REG_2_128TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CAP_REG_2_REG_VF_RESBAR_CAP_REG_2_128TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42880Up to 128TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RregisterDBI_Slave.PF0_VF_RESBAR_CAP.VF_RESBAR_CTRL_REG_2_REGVF_RESBAR_CTRL_REG_2_REGDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_BYTE_ADDRESSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_OFFSETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr432330x18R/W0x00000000DBI_Slave_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REGResizable BAR2 Control Register.For a description of this standard PCIe register, see the PCI Express Specification.falsefalsefalsefalseVF_RESBAR_CTRL_REG_IDX_2DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_IDX_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr42900BAR Index.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.200x0RRSVDP_3DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr42908Reserved for future use.430x0RVF_RESBAR_CTRL_REG_NUM_BARSDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_NUM_BARS_SETDWC_pcie_wire_cpcie_usp_4x8.csr42922Number of Resizeable BARs.For a description of this standard PCIe register field, see the PCI Express Specification.Note: This register field is sticky.750x0RVF_RESBAR_CTRL_REG_BAR_SIZEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_BAR_SIZE_SETDWC_pcie_wire_cpcie_usp_4x8.csr42936BAR Size.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 1380x00R/WRSVDP_14DBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr42944Reserved for future use.15140x0RVF_RESBAR_CTRL_REG_2_256TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42962Up to 256TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.16160x0RVF_RESBAR_CTRL_REG_2_512TBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512TB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42980Up to 512TB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.17170x0RVF_RESBAR_CTRL_REG_2_1PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr42998Up to 1PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.18180x0RVF_RESBAR_CTRL_REG_2_2PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr43016Up to 2PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.19190x0RVF_RESBAR_CTRL_REG_2_4PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr43034Up to 4PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.20200x0RVF_RESBAR_CTRL_REG_2_8PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr43052Up to 8PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.21210x0RVF_RESBAR_CTRL_REG_2_16PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_16PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr43070Up to 16PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.22220x0RVF_RESBAR_CTRL_REG_2_32PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_32PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr43088Up to 32PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.23230x0RVF_RESBAR_CTRL_REG_2_64PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_64PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr43106Up to 64PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.24240x0RVF_RESBAR_CTRL_REG_2_128PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_128PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr43124Up to 128PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.25250x0RVF_RESBAR_CTRL_REG_2_256PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_256PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr43142Up to 256PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.26260x0RVF_RESBAR_CTRL_REG_2_512PBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_512PB_SETDWC_pcie_wire_cpcie_usp_4x8.csr43160Up to 512PB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.27270x0RVF_RESBAR_CTRL_REG_2_1EBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_1EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr43178Up to 1EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.28280x0RVF_RESBAR_CTRL_REG_2_2EBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_2EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr43196Up to 2EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.29290x0RVF_RESBAR_CTRL_REG_2_4EBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_4EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr43214Up to 4EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.30300x0RVF_RESBAR_CTRL_REG_2_8EBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_WIDTHDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_MSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_LSBDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_RANGEDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_RESETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_FIELD_MASKDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_GETDBI_SLAVE_PF0_VF_RESBAR_CAP_VF_RESBAR_CTRL_REG_2_REG_VF_RESBAR_CTRL_REG_2_8EB_SETDWC_pcie_wire_cpcie_usp_4x8.csr43232Up to 8EB BAR Supported.For a description of this standard PCIe register field, see the PCI Express Specification.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.31310x0RgroupDBI_Slave.PF0_PORT_LOGICPF0_PORT_LOGICDBI_SLAVE_PF0_PORT_LOGIC_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr490760x700R/WDBI_Slave_PF0_PORT_LOGICPort LogicregisterDBI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFregisterDBI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFregisterDBI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFregisterDBI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFregisterDBI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFregisterDBI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFregisterDBI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFregisterDBI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFregisterDBI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFregisterDBI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFregisterDBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFregisterDBI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFregisterDBI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFregisterDBI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFregisterDBI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFregisterDBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFregisterDBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFregisterDBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFregisterDBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFregisterDBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFregisterDBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFregisterDBI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFregisterDBI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFregisterDBI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFregisterDBI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFregisterDBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFregisterDBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFregisterDBI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFregisterDBI_Slave.PF0_PORT_LOGIC.ACK_LATENCY_TIMER_OFFACK_LATENCY_TIMER_OFFDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr432910x0R/W0x0c23040bDBI_Slave_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFFAck Latency Timer and Replay Timer Register.falsefalsefalsefalseROUND_TRIP_LATENCY_TIME_LIMITDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_GETDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr43266Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details, see "Ack Scheduling".You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed.The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 3.0 specification.The limit must reflect the round trip latency from requester to completer.If there is a change in the payload size or link width, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.1500x040bR/WREPLAY_TIME_LIMITDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_GETDBI_SLAVE_PF0_PORT_LOGIC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr43290Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details, see "Transmit Replay".You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.After reset, the controller updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed.The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 3.0 specification.If there is a change in the payload size or link speed, the controller will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.31160x0c23R/WregisterDBI_Slave.PF0_PORT_LOGIC.VENDOR_SPEC_DLLP_OFFVENDOR_SPEC_DLLP_OFFDBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr433130x4R/W0xffffffffDBI_Slave_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFFVendor Specific DLLP Register.falsefalsefalsefalseVENDOR_SPEC_DLLPDBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MSBDBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_LSBDBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_RESETDBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_GETDBI_SLAVE_PF0_PORT_LOGIC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SETDWC_pcie_wire_cpcie_usp_4x8.csr43312Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP.Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register, then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to send the DLLP. - [7:0] = Type - [31:8] = Payload (24 bits)The dllp type is in bits [7:0] while the remainder is the vendor defined payload.Note: This register field is sticky.3100xffffffffR/WregisterDBI_Slave.PF0_PORT_LOGIC.PORT_FORCE_OFFPORT_FORCE_OFFDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr434070x8R/W0x00800004DBI_Slave_PF0_PORT_LOGIC_PORT_FORCE_OFFPort Force Link Register.falsefalsefalsefalseLINK_NUMDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_NUM_SETDWC_pcie_wire_cpcie_usp_4x8.csr43325Link Number. Not used for endpoint. Not used for M-PCIe.Note: This register field is sticky.700x04R/WFORCED_LTSSMDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCED_LTSSM_SETDWC_pcie_wire_cpcie_usp_4x8.csr43338Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link).Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v.Note: This register field is sticky.1180x0R/WRSVDP_12DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr43346Reserved for future use.14120x0RFORCE_ENDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_FORCE_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr43365Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state, and to force the controller to transmit a specific Link Command. Asserting this bit triggers the following actions: - Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the controller to transmit the command specified by the Forced Link Command field.This is a self-clearing register field. Reading from this register field always returns a "0".15150x0WLINK_STATEDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_LINK_STATE_SETDWC_pcie_wire_cpcie_usp_4x8.csr43377Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link).LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v.Note: This register field is sticky.21160x00R/WRSVDP_22DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr43385Reserved for future use.22220x0RDO_DESKEW_FOR_SRISDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SETDWC_pcie_wire_cpcie_usp_4x8.csr43398Use the transitions from TS2 to Logical Idle Symbol, SKP OS to Logical Idle Symbol, EIEOS to Logical Idle Symbol, and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS is set to 1.Note: This register field is sticky.23230x1R/WRSVDP_24DBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_FORCE_OFF_RSVDP_24_SETDWC_pcie_wire_cpcie_usp_4x8.csr43406Reserved for future use.31240x00RregisterDBI_Slave.PF0_PORT_LOGIC.ACK_F_ASPM_CTRL_OFFACK_F_ASPM_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr435340xCR/W0x1bc8c800DBI_Slave_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFFAck Frequency and L0-L1 ASPM Control Register.falsefalsefalsefalseACK_FREQDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_LSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_RANGEDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_RESETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_GETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr43435Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK request for every TLP that it receives. The controller waits until the ACK Latency Timer expires, then converts the current low-priority ACK request to a high-priority ACK request and schedules the DLLP for transmission to the remote link partner. - 1-255: Indicates that the controller will schedule a high-priority ACK after receiving this number of TLPs. It might schedule the ACK before receiving this number of TLPs if the ACK Latency Timer expires, but never later.For a typical system, you do not have to modify the default setting. For more details, see "ACK/NAK Scheduling".Note: This register field is sticky.700x00R/WACK_N_FTSDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_LSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_RESETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_GETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SETDWC_pcie_wire_cpcie_usp_4x8.csr43451N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255.The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.1580xc8R/WCOMMON_CLK_N_FTSDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_LSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_RESETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_GETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SETDWC_pcie_wire_cpcie_usp_4x8.csr43477Common Clock N_FTS. This is the N_FTS when common clock is used.The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. This field is only writable (sticky) when all of the following configuration parameter equations are true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCYThe controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 23160xc8RL0S_ENTRANCE_LATENCYDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_LSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_RANGEDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_RESETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_GETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SETDWC_pcie_wire_cpcie_usp_4x8.csr43494L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 usThis field is applicable to STALL while in L0 for M-PCIe.Note: This register field is sticky.26240x3R/WL1_ENTRANCE_LATENCYDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_LSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_RANGEDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_RESETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_GETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SETDWC_pcie_wire_cpcie_usp_4x8.csr43513L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 usNote: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite.Note: This register field is sticky.29270x3R/WENTER_ASPMDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_LSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_RANGEDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_RESETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_GETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SETDWC_pcie_wire_cpcie_usp_4x8.csr43525ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s.Note: This register field is sticky.30300x0R/WRSVDP_31DBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_MSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_LSBDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_RANGEDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_RESETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_GETDBI_SLAVE_PF0_PORT_LOGIC_ACK_F_ASPM_CTRL_OFF_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr43533Reserved for future use.31310x0RregisterDBI_Slave.PF0_PORT_LOGIC.PORT_LINK_CTRL_OFFPORT_LINK_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr437300x10R/W0x00000120DBI_Slave_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFFPort Link Control Register.falsefalsefalsefalseVENDOR_SPECIFIC_DLLP_REQDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr43551Vendor Specific DLLP Request. When software writes a '1' to this bit, the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF.Reading from this self-clearing register field always returns a '0'.000x0R/W1CSCRAMBLE_DISABLEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr43560Scramble Disable. Turns off data scrambling.Note: This register field is sticky.110x0R/WLOOPBACK_ENABLEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr43576Loopback Enable. Turns on loopback. For more details, see "Loopback".For M-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during Configuration.start state(initial discovery/configuration).M-PCIe doesn't support loopback mode from L0 state - only from Configuration.start.Note: This register field is sticky.220x0R/WRESET_ASSERTDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RESET_ASSERT_SETDWC_pcie_wire_cpcie_usp_4x8.csr43586Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only).Note: This register field is sticky.330x0R/WRSVDP_4DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr43594Reserved for future use.440x0RDLL_LINK_ENDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr43605DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the controller does not transmit InitFC DLLPs and does not establish a link.Note: This register field is sticky.550x1R/WLINK_DISABLEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr43614LINK_DISABLE is an internally reserved field. Do not use.Note: This register field is sticky.660x0R/WFAST_LINK_MODEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr43641Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster.The default scaling factor can be changed using the DEFAULT_FAST_LINK_SCALING_FACTOR parameter or through the FAST_LINK_SCALING_FACTOR field in the TIMER_CTRL_MAX_FUNC_NUM_OFF register.Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to '1'.For more details, see the "Fast Link Simulation Mode" section in the "Integrating the Controller with the PHY or Application RTL or Verification IP" chapter of the User Guide.For M-PCIe, this field also affects Remain Hibern8 Time, Minimum Activate Time, and RRAP timeout. If this bit is set to '1', tRRAPInitiatorResponse is set to 1.88 ms(60 ms/32).Note: This register field is sticky.770x0R/WLINK_RATEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_RATE_SETDWC_pcie_wire_cpcie_usp_4x8.csr43650LINK_RATE is an internally reserved field. Do not use.Note: This register field is sticky.1180x1R/WRSVDP_12DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr43658Reserved for future use.15120x0RLINK_CAPABLEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr43682Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing the link width, see "Link Establishment". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supported)This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.2116R/W--23220x0rBEACON_ENABLEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr43691BEACON_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.24240x0R/WCORRUPT_LCRC_ENABLEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr43701CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.25250x0R/WEXTENDED_SYNCHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SETDWC_pcie_wire_cpcie_usp_4x8.csr43711EXTENDED_SYNCH is an internally reserved field. Do not use.Note: This register field is sticky.26260x0R/WTRANSMIT_LANE_REVERSALE_ENABLEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr43721TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use.Note: This register field is sticky.27270x0R/WRSVDP_28DBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_MSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_LSBDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_RESETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_GETDBI_SLAVE_PF0_PORT_LOGIC_PORT_LINK_CTRL_OFF_RSVDP_28_SETDWC_pcie_wire_cpcie_usp_4x8.csr43729Reserved for future use.31280x0RregisterDBI_Slave.PF0_PORT_LOGIC.LANE_SKEW_OFFLANE_SKEW_OFFDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr438110x14R/W0x3c000000DBI_Slave_PF0_PORT_LOGIC_LANE_SKEW_OFFLane Skew Register.falsefalsefalsefalseINSERT_LANE_SKEWDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_MSBDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_LSBDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_RANGEDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_RESETDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_GETDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_INSERT_LANE_SKEW_SETDWC_pcie_wire_cpcie_usp_4x8.csr43743INSERT_LANE_SKEW is an internally reserved field. Do not use.Note: This register field is sticky.2300x000000R/WFLOW_CTRL_DISABLEDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr43753Flow Control Disable. Prevents the controller from sending FC DLLPs.Note: This register field is sticky.24240x0R/WACK_NAK_DISABLEDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ACK_NAK_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr43763Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs.Note: This register field is sticky.25250x0R/WELASTIC_BUFFER_MODEDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr43774Selects Elasticity Buffer operating mode:0: Nominal Half Full Buffer mode1: Nominal Empty Buffer ModeNote: This register field is sticky.26260x1R/WIMPLEMENT_NUM_LANESDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_MSBDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_LSBDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_RANGEDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_RESETDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_GETDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_SETDWC_pcie_wire_cpcie_usp_4x8.csr43800Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanesThe number of lanes to be used when in Loopback Master. The number of lanes programmed must be equal to or less than the valid number of lanes set in LINK_CAPABLE field. You must configure this field before initiating Loopback by writing in the LOOPBACK_ENABLE field.The controller will transition from Loopback.Entry to Loopback.Active after receiving two consecutive TS1 Ordered Sets with the Loopback bit asserted on the implementation specific number of lanes configured in this field.Note: This register field is sticky.30270x7R/WDISABLE_LANE_TO_LANE_DESKEWDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_MSBDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_LSBDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_RANGEDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_RESETDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_GETDBI_SLAVE_PF0_PORT_LOGIC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_SETDWC_pcie_wire_cpcie_usp_4x8.csr43810Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic.Note: This register field is sticky.31310x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.TIMER_CTRL_MAX_FUNC_NUM_OFFTIMER_CTRL_MAX_FUNC_NUM_OFFDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr439080x18R/W0x40000000DBI_Slave_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFFTimer Control and Max Function Number Register.falsefalsefalsefalseMAX_FUNC_NUMDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_LSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_RESETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_GETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SETDWC_pcie_wire_cpcie_usp_4x8.csr43825Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request).Note: This register field is sticky.700x00R/WRSVDP_8DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_MSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_LSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_RESETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_GETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr43833Reserved for future use.1380x00RTIMER_MOD_REPLAY_TIMERDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_LSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_RESETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_GETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SETDWC_pcie_wire_cpcie_usp_4x8.csr43853Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed. A value of "0" represents no modification to the timer limit. For more details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.At Gen3 speed, the controller automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ.For M-PCIe, this field increases the time-out value for the replay timer in increments of 64 clock cycles at HS-Gear1, HS-Gear2, or HS-Gear3 speed.Note: This register field is sticky.1814R/WTIMER_MOD_ACK_NAKDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_LSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_RESETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_GETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SETDWC_pcie_wire_cpcie_usp_4x8.csr43867Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of "0" represents no modification to the timer value. For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.Note: This register field is sticky.23190x00R/WUPDATE_FREQ_TIMERDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_LSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_RESETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_GETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SETDWC_pcie_wire_cpcie_usp_4x8.csr43877UPDATE_FREQ_TIMER is an internally reserved field. Do not use.Note: This register field is sticky.28240x00R/WFAST_LINK_SCALING_FACTORDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_LSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_RESETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_GETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr43899Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Factor is 64 (1ms is 16us) - 3: Scaling Factor is 16 (1ms is 64us)Default is set by the hidden configuration parameter DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0'.*a. When the LTSSM is in Config or L12 Entry State, 1ms timer is 2us, 2ms timer is 4us and 3ms timer is 6us.Not used for M-PCIe. Note: This register field is sticky.30290x2R/WRSVDP_31DBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_MSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_LSBDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_RESETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_GETDBI_SLAVE_PF0_PORT_LOGIC_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr43907Reserved for future use.31310x0RregisterDBI_Slave.PF0_PORT_LOGIC.SYMBOL_TIMER_FILTER_1_OFFSYMBOL_TIMER_FILTER_1_OFFDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr440650x1CR/W0x00000140DBI_Slave_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFFSymbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.falsefalsefalsefalseSKP_INT_VALDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MSBDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_LSBDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_RANGEDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_RESETDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_GETDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SETDWC_pcie_wire_cpcie_usp_4x8.csr43947SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register (in a 250 MHz controller), then the controller actually transmits SKP ordered sets once every 1537 symbol times.The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz controller, programming the value programmed to this register should be scaled down by a factor of 2 (because one clock tick = two symbol times in this case).Note: This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks.For M-PCIe configurations, if the 2K_PPM_DISABLED field in the M-PCIe Configuration Attribute is changed, then this field is changed automatically as follows. - 2K_PPM_DISABLED=1: 1280 / CX_NB - 2K_PPM_DISABLED=0: 228/CX_NBYou need to set this field again if necessary when 2K_PPM_DISABLED is changed.Note: This register field is sticky.1000x140R/WEIDLE_TIMERDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MSBDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_LSBDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_RANGEDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_RESETDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_GETDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SETDWC_pcie_wire_cpcie_usp_4x8.csr43956EIDLE_TIMER is an internally reserved field. Do not use.Note: This register field is sticky.14110x0R/WDISABLE_FC_WD_TIMERDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MSBDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_LSBDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_RANGEDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_RESETDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_GETDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SETDWC_pcie_wire_cpcie_usp_4x8.csr43965Disable FC Watchdog Timer.Note: This register field is sticky.15150x0R/WMASK_RADM_1DBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MSBDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_LSBDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_RESETDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_GETDBI_SLAVE_PF0_PORT_LOGIC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr44064Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.[31]: CX_FLT_MASK_RC_CFG_DISCARD - 0: For RADM RC filter to not allow CFG transaction being received - 1: For RADM RC filter to allow CFG transaction being received[30]: CX_FLT_MASK_RC_IO_DISCARD - 0: For RADM RC filter to not allow IO transaction being received - 1: For RADM RC filter to allow IO transaction being received[29]: CX_FLT_MASK_MSG_DROP - 0: Drop MSG TLP (except for Vendor MSG). Send decoded message on the SII. - 1: Do not Drop MSG (except for Vendor MSG). Send message TLPs to your application on TRGT1 and send decoded message on the SII. - The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG =1, then the default of this bit is "0" (drop message TLPs). This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The controller never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The controller passes all ATS Invalidate messages to TRGT1 (or AXI bridge master), as they are too big for the SII.[28]: CX_FLT_MASK_CPL_ECRC_DISCARD - Only used when completion queue is advertised with infinite credits and is in store-and-forward mode. - 0: Discard completions with ECRC errors - 1: Allow completions with ECRC errors to be passed up - Reserved field for SW.[27]: CX_FLT_MASK_ECRC_DISCARD - 0: Discard TLPs with ECRC errors - 1: Allow TLPs with ECRC errors to be passed up[26]: CX_FLT_MASK_CPL_LEN_MATCH - 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err - 1: MASK length match for completions[25]: CX_FLT_MASK_CPL_ATTR_MATCH - 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask attribute match for completions[24]: CX_FLT_MASK_CPL_TC_MATCH - 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Traffic Class match for completions[23]: CX_FLT_MASK_CPL_FUNC_MATCH - 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask function match for completions[22]: CX_FLT_MASK_CPL_REQID_MATCH - 0: Enforce Req. Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Req. Id match for completions[21]: CX_FLT_MASK_CPL_TAGERR_MATCH - 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Tag Error Rules for completions[20]: CX_FLT_MASK_LOCKED_RD_AS_UR - 0: Treat locked Read TLPs as UR for EP; Supported for RC - 1: Treat locked Read TLPs as Supported for EP; UR for RC[19]: CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR - 0: Treat CFG type1 TLPs as UR for EP; Supported for RC - 1: Treat CFG type1 TLPs as Supported for EP; UR for RC - When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests if the EP consumes more than one bus number.[18]: CX_FLT_MASK_UR_OUTSIDE_BAR - 0: Treat out-of-bar TLPs as UR - 1: Do not treat out-of-bar TLPs as UR[17]: CX_FLT_MASK_UR_POIS - 0: Treat poisoned request TLPs as UR - 1: Do not treat poisoned request TLPs as UR - The native controller always passes poisoned completions to your application except when you are using the DMA read channel.[16]: CX_FLT_MASK_UR_FUNC_MISMATCH - 0: Treat Function MisMatched TLPs as UR - 1: Do not treat Function MisMatched TLPs as URNote: This register field is sticky.31160x0000R/WregisterDBI_Slave.PF0_PORT_LOGIC.FILTER_MASK_2_OFFFILTER_MASK_2_OFFDBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr441260x20R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_FILTER_MASK_2_OFFFilter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.falsefalsefalsefalseMASK_RADM_2DBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_MSBDBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_LSBDBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_RANGEDBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_RESETDBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_GETDBI_SLAVE_PF0_PORT_LOGIC_FILTER_MASK_2_OFF_MASK_RADM_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr44125Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.[31:10]: Reserved[9]: CX_FLT_MASK_CPL_IN_LUT_CHECK - 0: Disable masking of checking if the tag of CPL is registered in LUT - 1: Enable masking of checking if the tag of CPL is registered in LUT[8]: CX_FLT_MASK_POIS_ERROR_REPORTING - 0: Disable masking of error reporting for Poisoned TLPs - 1: Enable masking of error reporting for Poisoned TLPs[7]: CX_FLT_MASK_PRS_DROP - 0: Allow PRS message to pass through - 1: Drop PRS Messages silently - This bit is ignored when the CX_FLT_MASK_MSG_DROP bit in the MASK_RADM_1 field of the SYMBOL_TIMER_FILTER_1_OFF register is set to '1'.[6]: CX_FLT_UNMASK_TD - 0: Disable unmask TD bit if CX_STRIP_ECRC_ENABLE - 1: Enable unmask TD bit if CX_STRIP_ECRC_ENABLE[5]: CX_FLT_UNMASK_UR_POIS_TRGT0 - 0: Disable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination - 1: Enable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination[4]: CX_FLT_MASK_LN_VENMSG1_DROP - 0: Allow LN message to pass through - 1: Drop LN Messages silently[3]: CX_FLT_MASK_HANDLE_FLUSH - 0: Disable controller Filter to handle flush request - 1: Enable controller Filter to handle flush request[2]: CX_FLT_MASK_DABORT_4UCPL - 0: Enable DLLP abort for unexpected completion - 1: Do not enable DLLP abort for unexpected completion[1]: CX_FLT_MASK_VENMSG1_DROP - 0: Vendor MSG Type 1 dropped silently - 1: Vendor MSG Type 1 not dropped[0]: CX_FLT_MASK_VENMSG0_DROP - 0: Vendor MSG Type 0 dropped with UR error reporting - 1: Vendor MSG Type 0 not droppedNote: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFAMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr441600x24R/W0x00000001DBI_Slave_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFFAMBA Multiple Outbound Decomposed NP SubRequests Control Register.falsefalsefalsefalseOB_RD_SPLIT_BURST_ENDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr44151Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to "0" disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more details, see "AXI Bridge Ordering" in the AXI chapter of the Databook.You should not clear this register unless your application master is requesting an amount of read data greater than Max_Read_Request_Size, and the remote device (or switch) is reordering completions that have different tags.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.000x1R/WRSVDP_1DBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr44159Reserved for future use.3110x00000000RregisterDBI_Slave.PF0_PORT_LOGIC.PL_DEBUG0_OFFPL_DEBUG0_OFFDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr441730x28RDBI_Slave_PF0_PORT_LOGIC_PL_DEBUG0_OFFDebug Register 0falsefalsefalsefalseDEB_REG_0DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_MSBDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_LSBDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_RESETDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_GETDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG0_OFF_DEB_REG_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr44172The value on cxpl_debug_info[31:0].310RregisterDBI_Slave.PF0_PORT_LOGIC.PL_DEBUG1_OFFPL_DEBUG1_OFFDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr441860x2CRDBI_Slave_PF0_PORT_LOGIC_PL_DEBUG1_OFFDebug Register 1falsefalsefalsefalseDEB_REG_1DBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_MSBDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_LSBDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_RESETDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_GETDBI_SLAVE_PF0_PORT_LOGIC_PL_DEBUG1_OFF_DEB_REG_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr44185The value on cxpl_debug_info[63:32].310RregisterDBI_Slave.PF0_PORT_LOGIC.TX_P_FC_CREDIT_STATUS_OFFTX_P_FC_CREDIT_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr442400x30R0x00000000DBI_Slave_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFFTransmit Posted FC Credit StatusfalsefalsefalsefalseTX_P_DATA_FC_CREDITDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44211Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_P_HEADER_FC_CREDITDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44232Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_P_FC_CREDIT_STATUSDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_MSBDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_LSBDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_RESETDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_GETDBI_SLAVE_PF0_PORT_LOGIC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr44239Reserved for future use.31280x0RregisterDBI_Slave.PF0_PORT_LOGIC.TX_NP_FC_CREDIT_STATUS_OFFTX_NP_FC_CREDIT_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr442940x34R0x00000000DBI_Slave_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFFTransmit Non-Posted FC Credit StatusfalsefalsefalsefalseTX_NP_DATA_FC_CREDITDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44265Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_NP_HEADER_FC_CREDITDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44286Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised non-posted credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_NP_FC_CREDIT_STATUSDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_MSBDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_LSBDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_RESETDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_GETDBI_SLAVE_PF0_PORT_LOGIC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr44293Reserved for future use.31280x0RregisterDBI_Slave.PF0_PORT_LOGIC.TX_CPL_FC_CREDIT_STATUS_OFFTX_CPL_FC_CREDIT_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr443480x38R0x00000000DBI_Slave_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFFTransmit Completion FC Credit StatusfalsefalsefalsefalseTX_CPL_DATA_FC_CREDITDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44319Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].1500x0000RTX_CPL_HEADER_FC_CREDITDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44340Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.Default value depends on the number of advertised credits for header and dataScaled Flow Control: [4'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [4'b0, 12'hFFF, 16'hFFFF].No Scaling: [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].27160x000RRSVDP_TX_CPL_FC_CREDIT_STATUSDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_MSBDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_LSBDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_RESETDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_GETDBI_SLAVE_PF0_PORT_LOGIC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr44347Reserved for future use.31280x0RregisterDBI_Slave.PF0_PORT_LOGIC.QUEUE_STATUS_OFFQUEUE_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr444520x3CR/W0x00000000DBI_Slave_PF0_PORT_LOGIC_QUEUE_STATUS_OFFQueue StatusfalsefalsefalsefalseRX_TLP_FC_CREDIT_NON_RETURNDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_LSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_RESETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_GETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SETDWC_pcie_wire_cpcie_usp_4x8.csr44365Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the link.000x0RTX_RETRY_BUFFER_NEDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_LSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_RESETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_GETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44376Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer.110x0RRX_QUEUE_NON_EMPTYDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_LSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_RANGEDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_RESETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_GETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SETDWC_pcie_wire_cpcie_usp_4x8.csr44387Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers.220x0RRX_QUEUE_OVERFLOWDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_LSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_RANGEDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_RESETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_GETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SETDWC_pcie_wire_cpcie_usp_4x8.csr44398Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue.330x0R/W1CRSVDP_4DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_MSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_LSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_RANGEDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_RESETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_GETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr44406Reserved for future use.1240x000RRX_SERIALIZATION_Q_NON_EMPTYDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_LSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_RANGEDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_RESETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_GETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SETDWC_pcie_wire_cpcie_usp_4x8.csr44417Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue.13130x0R--15140x0rTIMER_MOD_FLOW_CONTROLDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_LSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_RANGEDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_RESETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_GETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SETDWC_pcie_wire_cpcie_usp_4x8.csr44430FC Latency Timer Override Value. When you set the "FC Latency Timer Override Enable" in this register, the value in this field will override the FC latency timer value that the controller calculates according to the PCIe specification. For more details, see "Flow Control".Note: This register field is sticky.28160x0000R/WRSVDP_29DBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_MSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_LSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_RANGEDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_RESETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_GETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr44438Reserved for future use.30290x0RTIMER_MOD_FLOW_CONTROL_ENDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr44451FC Latency Timer Override Enable. When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will override the FC latency timer value that the controller calculates according to the PCIe specification.Note: This register field is sticky.31310x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_1_OFFVC_TX_ARBI_1_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr445010x40R0x0000000fDBI_Slave_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFFVC Transmit Arbitration Register 1falsefalsefalsefalseWRR_WEIGHT_VC_0DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_GETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr44467WRR Weight for VC0.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 700x0fRWRR_WEIGHT_VC_1DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_GETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr44478WRR Weight for VC1.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 1580x00RWRR_WEIGHT_VC_2DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_GETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr44489WRR Weight for VC2.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 23160x00RWRR_WEIGHT_VC_3DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_GETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr44500WRR Weight for VC3.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 31240x00RregisterDBI_Slave.PF0_PORT_LOGIC.VC_TX_ARBI_2_OFFVC_TX_ARBI_2_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr445500x44R0x00000000DBI_Slave_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFFVC Transmit Arbitration Register 2falsefalsefalsefalseWRR_WEIGHT_VC_4DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_GETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_SETDWC_pcie_wire_cpcie_usp_4x8.csr44516WRR Weight for VC4.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 700x00RWRR_WEIGHT_VC_5DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_GETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr44527WRR Weight for VC5.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 1580x00RWRR_WEIGHT_VC_6DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_GETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr44538WRR Weight for VC6.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 23160x00RWRR_WEIGHT_VC_7DBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_GETDBI_SLAVE_PF0_PORT_LOGIC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr44549WRR Weight for VC7.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R 31240x00RregisterDBI_Slave.PF0_PORT_LOGIC.VC0_P_RX_Q_CTRL_OFFVC0_P_RX_Q_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr446540x48R/W0x462602e0DBI_Slave_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFFSegmented-Buffer VC0 Posted Receive Queue Control.falsefalsefalsefalseVC0_P_DATA_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44567VC0 Posted Data Credits. The number of initial posted data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC0_P_HEADER_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44581VC0 Posted Header Credits. The number of initial posted header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED4DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SETDWC_pcie_wire_cpcie_usp_4x8.csr44590Reserved.Note: This register field is sticky.20200x0R/WVC0_P_TLP_Q_MODEDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44599Reserved.Note: This register field is sticky.23210x1R/WVC0_P_HDR_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44609VC0 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC0_P_DATA_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44619VC0 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED5DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SETDWC_pcie_wire_cpcie_usp_4x8.csr44628Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC0DBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SETDWC_pcie_wire_cpcie_usp_4x8.csr44640TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WVC_ORDERING_RX_QDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SETDWC_pcie_wire_cpcie_usp_4x8.csr44653VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0: Round robinNote: This register field is sticky.31310x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.VC0_NP_RX_Q_CTRL_OFFVC0_NP_RX_Q_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr447330x4CR/W0x06260060DBI_Slave_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFFSegmented-Buffer VC0 Non-Posted Receive Queue Control.falsefalsefalsefalseVC0_NP_DATA_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44671VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x060R/WVC0_NP_HEADER_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44685VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED6DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SETDWC_pcie_wire_cpcie_usp_4x8.csr44694Reserved.Note: This register field is sticky.20200x0R/WVC0_NP_TLP_Q_MODEDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44703Reserved.Note: This register field is sticky.23210x1R/WVC0_NP_HDR_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44713VC0 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC0_NP_DATA_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44723VC0 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED7DBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SETDWC_pcie_wire_cpcie_usp_4x8.csr44732Reserved.Note: This register field is sticky.31280x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.VC0_CPL_RX_Q_CTRL_OFFVC0_CPL_RX_Q_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr448120x50R/W0x06200000DBI_Slave_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC0 Completion Receive Queue Control.falsefalsefalsefalseVC0_CPL_DATA_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44750VC0 Completion Data Credits. The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC0_CPL_HEADER_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44764VC0 Completion Header Credits. The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED8DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SETDWC_pcie_wire_cpcie_usp_4x8.csr44773Reserved.Note: This register field is sticky.20200x0R/WVC0_CPL_TLP_Q_MODEDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44782Reserved.Note: This register field is sticky.23210x1R/WVC0_CPL_HDR_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44792VC0 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC0_CPL_DATA_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44802VC0 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED9DBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_GETDBI_SLAVE_PF0_PORT_LOGIC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SETDWC_pcie_wire_cpcie_usp_4x8.csr44811Reserved.Note: This register field is sticky.31280x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.VC1_P_RX_Q_CTRL_OFFVC1_P_RX_Q_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr449120x54R/W0x462602e0DBI_Slave_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC1_P_DATA_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44829VC1 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC1_P_HEADER_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44843VC1 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC1DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED0_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr44852Reserved.Note: This register field is sticky.20200x0R/WVC1_P_TLP_Q_MODEDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44861Reserved.Note: This register field is sticky.23210x1R/WVC1_P_HDR_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44871VC1 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC1_P_DATA_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_VC1_P_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44881VC1 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC1DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED1_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr44890Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC1DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr44902TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC1DBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_P_RX_Q_CTRL_OFF_RESERVED2_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr44911Reserved.Note: This register field is sticky.31310x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.VC1_NP_RX_Q_CTRL_OFFVC1_NP_RX_Q_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr449910x58R/W0x06260001DBI_Slave_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC1_NP_DATA_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44929VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC1_NP_HEADER_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr44943VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC1DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED3_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr44952Reserved.Note: This register field is sticky.20200x0R/WVC1_NP_TLP_Q_MODEDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44961Reserved.Note: This register field is sticky.23210x1R/WVC1_NP_HDR_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44971VC1 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC1_NP_DATA_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_VC1_NP_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr44981VC1 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC1DBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_NP_RX_Q_CTRL_OFF_RESERVED4_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr44990Reserved.Note: This register field is sticky.31280x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.VC1_CPL_RX_Q_CTRL_OFFVC1_CPL_RX_Q_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr450700x5CR/W0x06200000DBI_Slave_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC1_CPL_DATA_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45008VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC1_CPL_HEADER_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45022VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC1DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED5_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr45031Reserved.Note: This register field is sticky.20200x0R/WVC1_CPL_TLP_Q_MODEDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45040Reserved.Note: This register field is sticky.23210x1R/WVC1_CPL_HDR_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45050VC1 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC1_CPL_DATA_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_VC1_CPL_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45060VC1 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC1DBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_GETDBI_SLAVE_PF0_PORT_LOGIC_VC1_CPL_RX_Q_CTRL_OFF_RESERVED6_VC1_SETDWC_pcie_wire_cpcie_usp_4x8.csr45069Reserved.Note: This register field is sticky.31280x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.VC2_P_RX_Q_CTRL_OFFVC2_P_RX_Q_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr451700x60R/W0x462602e0DBI_Slave_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC2_P_DATA_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45087VC2 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC2_P_HEADER_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45101VC2 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC2DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED0_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr45110Reserved.Note: This register field is sticky.20200x0R/WVC2_P_TLP_Q_MODEDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45119Reserved.Note: This register field is sticky.23210x1R/WVC2_P_HDR_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45129VC2 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC2_P_DATA_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_VC2_P_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45139VC2 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC2DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED1_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr45148Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC2DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr45160TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC2DBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_P_RX_Q_CTRL_OFF_RESERVED2_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr45169Reserved.Note: This register field is sticky.31310x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.VC2_NP_RX_Q_CTRL_OFFVC2_NP_RX_Q_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr452490x64R/W0x06260001DBI_Slave_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC2_NP_DATA_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45187VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC2_NP_HEADER_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45201VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC2DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED3_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr45210Reserved.Note: This register field is sticky.20200x0R/WVC2_NP_TLP_Q_MODEDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45219Reserved.Note: This register field is sticky.23210x1R/WVC2_NP_HDR_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45229VC2 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC2_NP_DATA_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_VC2_NP_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45239VC2 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC2DBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_NP_RX_Q_CTRL_OFF_RESERVED4_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr45248Reserved.Note: This register field is sticky.31280x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.VC2_CPL_RX_Q_CTRL_OFFVC2_CPL_RX_Q_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr453280x68R/W0x06200000DBI_Slave_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC2_CPL_DATA_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45266VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC2_CPL_HEADER_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45280VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC2DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED5_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr45289Reserved.Note: This register field is sticky.20200x0R/WVC2_CPL_TLP_Q_MODEDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45298Reserved.Note: This register field is sticky.23210x1R/WVC2_CPL_HDR_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45308VC2 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC2_CPL_DATA_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_VC2_CPL_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45318VC2 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC2DBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_GETDBI_SLAVE_PF0_PORT_LOGIC_VC2_CPL_RX_Q_CTRL_OFF_RESERVED6_VC2_SETDWC_pcie_wire_cpcie_usp_4x8.csr45327Reserved.Note: This register field is sticky.31280x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.VC3_P_RX_Q_CTRL_OFFVC3_P_RX_Q_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr454280x6CR/W0x462602e0DBI_Slave_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFFSegmented-Buffer VC#i Posted Receive Queue Control.falsefalsefalsefalseVC3_P_DATA_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45345VC3 Posted Data Credits. The number of initial posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x2e0R/WVC3_P_HEADER_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45359VC3 Posted Header Credits. The number of initial posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED0_VC3DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED0_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr45368Reserved.Note: This register field is sticky.20200x0R/WVC3_P_TLP_Q_MODEDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45377Reserved.Note: This register field is sticky.23210x1R/WVC3_P_HDR_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45387VC3 Scale Posted Header Credites.Note: This register field is sticky.25240x2R/WVC3_P_DATA_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_VC3_P_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45397VC3 Scale Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED1_VC3DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED1_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr45406Reserved.Note: This register field is sticky.29280x0R/WTLP_TYPE_ORDERING_VC3DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr45418TLP Type Ordering for VC#i. Determines the TLP type ordering rule for VC#i receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-postedNote: This register field is sticky.30300x1R/WRESERVED2_VC3DBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_P_RX_Q_CTRL_OFF_RESERVED2_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr45427Reserved.Note: This register field is sticky.31310x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.VC3_NP_RX_Q_CTRL_OFFVC3_NP_RX_Q_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr455070x70R/W0x06260001DBI_Slave_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFFSegmented-Buffer VC#i Non-Posted Receive Queue Control.falsefalsefalsefalseVC3_NP_DATA_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45445VC#i Non-Posted Data Credits. The number of initial non-posted data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x001R/WVC3_NP_HEADER_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45459VC#i Non-Posted Header Credits. The number of initial non-posted header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x60R/WRESERVED3_VC3DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED3_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr45468Reserved.Note: This register field is sticky.20200x0R/WVC3_NP_TLP_Q_MODEDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45477Reserved.Note: This register field is sticky.23210x1R/WVC3_NP_HDR_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45487VC3 Scale Non-Posted Header Credites.Note: This register field is sticky.25240x2R/WVC3_NP_DATA_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_VC3_NP_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45497VC3 Scale Non-Posted Data Credites.Note: This register field is sticky.27260x1R/WRESERVED4_VC3DBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_NP_RX_Q_CTRL_OFF_RESERVED4_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr45506Reserved.Note: This register field is sticky.31280x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.VC3_CPL_RX_Q_CTRL_OFFVC3_CPL_RX_Q_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr455860x74R/W0x06200000DBI_Slave_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFFSegmented-Buffer VC#i Completion Receive Queue Control.falsefalsefalsefalseVC3_CPL_DATA_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45524VC#i Completion Data Credits. The number of initial Completion data credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.1100x000R/WVC3_CPL_HEADER_CREDITDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HEADER_CREDIT_SETDWC_pcie_wire_cpcie_usp_4x8.csr45538VC#i Completion Header Credits. The number of initial Completion header credits for VC#i, used only in the segmented-buffer configuration.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R (sticky) Note: This register field is sticky.19120x00R/WRESERVED5_VC3DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED5_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr45547Reserved.Note: This register field is sticky.20200x0R/WVC3_CPL_TLP_Q_MODEDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_TLP_Q_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45556Reserved.Note: This register field is sticky.23210x1R/WVC3_CPL_HDR_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_HDR_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45566VC3 Scale CPL Header Credites.Note: This register field is sticky.25240x2R/WVC3_CPL_DATA_SCALEDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_VC3_CPL_DATA_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45576VC3 Scale CPL Data Credites.Note: This register field is sticky.27260x1R/WRESERVED6_VC3DBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_MSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_LSBDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_RANGEDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_RESETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_GETDBI_SLAVE_PF0_PORT_LOGIC_VC3_CPL_RX_Q_CTRL_OFF_RESERVED6_VC3_SETDWC_pcie_wire_cpcie_usp_4x8.csr45585Reserved.Note: This register field is sticky.31280x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.GEN2_CTRL_OFFGEN2_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr45872Link Width and Speed Change Control Register.0x10CR/W0x000108c8DBI_Slave_PF0_PORT_LOGIC_GEN2_CTRL_OFFThis register is used to control various functions of the controller related to link training, lane reversal, and equalization.falsefalsefalsefalseFAST_TRAINING_SEQDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr45613Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state. The number should be provided by the PHY vendor. Do not set N_FTS to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0s.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.700xc8R/WNUM_OF_LANESDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_NUM_OF_LANES_SETDWC_pcie_wire_cpcie_usp_4x8.csr45653Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured. This value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI Express Base 3.0 Specification, revision 1.0. Encoding is as follows: - 0x01: 1 lane - 0x02: 2 lanes - 0x03: 3 lanes - ..When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Link Mode Enable" field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as the encoded value in PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then you must reduce the value in this register. For more information, see "How to Tie Off Unused Lanes." For information on upsizing and downsizing the link width, see "Link Establishment."This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.1280x08R/WPRE_DET_LANEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_PRE_DET_LANE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45703Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect.This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state.Note: This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.15130x0R/WfalsetruefalseLANE00x0Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1, depending on which lane is detectedLANE10x1Connect logical Lane0 to physical lane 1LANE150x4Connect logical Lane0 to physical lane 15LANE30x2Connect logical Lane0 to physical lane 3LANE70x3connect logical lane0 to physical lane 7AUTO_LANE_FLIP_CTRL_ENDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr45721Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details, see the 'Lane Reversal' appendix in the Databook. This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.16160x1R/WDIRECT_SPEED_CHANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45754Directed Speed Change. Writing "1" to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed.When the speed change occurs, the controller will clear the contents of this field; and a read to this field by your software will return a "0".To manually initiate the speed change: - Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this fieldIf you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1", then the speed change is initiated automatically after link up, and the controller clears the contents of this field. If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF . PCIE_CAP_TARGET_LINK_SPEED) through the DBI before link up.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W - Dbi: R/W 17170x0R/WCONFIG_PHY_TX_CHANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45771Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low SwingThis field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.18180x0R/WCONFIG_TX_COMP_RXDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SETDWC_pcie_wire_cpcie_usp_4x8.csr45786Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to "1").This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.19190x0R/WSEL_DEEMPHASISDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SETDWC_pcie_wire_cpcie_usp_4x8.csr45802Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dBThis field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.20200x0R/WGEN1_EI_INFERENCEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr45820Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be inferred successfully in the controller by just detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical IdleNote: This register field is sticky.21210x0R/WRSVDP_22DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr45828Reserved for future use.23220x0RLANE_UNDER_TESTDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_LANE_UNDER_TEST_SETDWC_pcie_wire_cpcie_usp_4x8.csr45845The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.27240x0R--29280x0rFORCE_LANE_FLIPDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_SETDWC_pcie_wire_cpcie_usp_4x8.csr45863Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1.This field is reserved (fixed to '0') for M-PCIe.Note: The access attributes of this field are as follows: - Wire: R (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.30300x0RRSVDP_31DBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN2_CTRL_OFF_RSVDP_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr45871Reserved for future use.31310x0RregisterDBI_Slave.PF0_PORT_LOGIC.PHY_STATUS_OFFPHY_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr458960x110RDBI_Slave_PF0_PORT_LOGIC_PHY_STATUS_OFFPHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins.falsefalsefalsefalsePHY_STATUSDBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_MSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_LSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_RESETDBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_GETDBI_SLAVE_PF0_PORT_LOGIC_PHY_STATUS_OFF_PHY_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr45895PHY Status. Data received directly from the phy_cfg_status bus.These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller functionality. You can use it for any static sideband status signalling requirements that you have for your PHY.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.310RregisterDBI_Slave.PF0_PORT_LOGIC.PHY_CONTROL_OFFPHY_CONTROL_OFFDBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr459180x114R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_PHY_CONTROL_OFFPHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins.falsefalsefalsefalsePHY_CONTROLDBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_MSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_LSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_RESETDBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_GETDBI_SLAVE_PF0_PORT_LOGIC_PHY_CONTROL_OFF_PHY_CONTROL_SETDWC_pcie_wire_cpcie_usp_4x8.csr45917PHY Control. Data sent directly to the cfg_phy_control bus.These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller functionality. You can use it for any static sideband control signalling requirements that you have for your PHY.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.TRGT_MAP_CTRL_OFFTRGT_MAP_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr459770x11CR/W0x0000006fDBI_Slave_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFFProgrammable Target Map Control Register.falsefalsefalsefalseTARGET_MAP_PFDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_LSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_RESETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_GETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SETDWC_pcie_wire_cpcie_usp_4x8.csr45931Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits.500x2fR/WTARGET_MAP_ROMDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_LSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_RESETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_GETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SETDWC_pcie_wire_cpcie_usp_4x8.csr45942Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits.660x1R/W--1270x0rTARGET_MAP_RESERVED_13_15DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_LSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_RESETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_GETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr45954Reserved.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R (sticky) 15130x0RTARGET_MAP_INDEXDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_LSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_RESETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_GETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SETDWC_pcie_wire_cpcie_usp_4x8.csr45964The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits.20160x00R/WTARGET_MAP_RESERVED_21_31DBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_LSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_RESETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_GETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr45976Reserved.Note: The access attributes of this field are as follows: - Wire: RSVDP - Dbi: R (sticky) 31210x000RregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_ADDR_OFFMSI_CTRL_ADDR_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr459970x120R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFFIntegrated MSI Reception Module (iMRM) Address Register.falsefalsefalsefalseMSI_CTRL_ADDRDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_SETDWC_pcie_wire_cpcie_usp_4x8.csr45996Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination.Within the AXI Bridge, every received Memory Write request is examined to see if it targets the MSI Address that has been specified in this register; and also to see if it satisfies the definition of an MSI interrupt request. When these conditions are satisfied the Memory Write request is marked as an MSI request.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_UPPER_ADDR_OFFMSI_CTRL_UPPER_ADDR_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr460130x124R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFFIntegrated MSI Reception Module Upper Address Register.falsefalsefalsefalseMSI_CTRL_UPPER_ADDRDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_SETDWC_pcie_wire_cpcie_usp_4x8.csr46012Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_EN_OFFMSI_CTRL_INT_0_EN_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr460300x128R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_0_ENDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr46029MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_MASK_OFFMSI_CTRL_INT_0_MASK_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr460480x12CR/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_0_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr46047MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_0_STATUS_OFFMSI_CTRL_INT_0_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr460660x130R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_0_STATUSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr46065MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_EN_OFFMSI_CTRL_INT_1_EN_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr460830x134R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_1_ENDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr46082MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_MASK_OFFMSI_CTRL_INT_1_MASK_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr461010x138R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_1_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr46100MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_1_STATUS_OFFMSI_CTRL_INT_1_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr461190x13CR/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_1_STATUSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr46118MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_EN_OFFMSI_CTRL_INT_2_EN_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr461360x140R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_2_ENDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr46135MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_MASK_OFFMSI_CTRL_INT_2_MASK_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr461540x144R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_2_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr46153MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_2_STATUS_OFFMSI_CTRL_INT_2_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr461720x148R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_2_STATUSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr46171MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_EN_OFFMSI_CTRL_INT_3_EN_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr461890x14CR/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_3_ENDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr46188MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_MASK_OFFMSI_CTRL_INT_3_MASK_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr462070x150R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_3_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr46206MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_3_STATUS_OFFMSI_CTRL_INT_3_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr462250x154R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_3_STATUSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr46224MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_EN_OFFMSI_CTRL_INT_4_EN_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr462420x158R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_4_ENDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr46241MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_MASK_OFFMSI_CTRL_INT_4_MASK_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr462600x15CR/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_4_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr46259MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_4_STATUS_OFFMSI_CTRL_INT_4_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr462780x160R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_4_STATUSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr46277MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_EN_OFFMSI_CTRL_INT_5_EN_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr462950x164R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_5_ENDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr46294MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_MASK_OFFMSI_CTRL_INT_5_MASK_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr463130x168R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_5_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr46312MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_5_STATUS_OFFMSI_CTRL_INT_5_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr463310x16CR/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_5_STATUSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr46330MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_EN_OFFMSI_CTRL_INT_6_EN_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr463480x170R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_6_ENDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr46347MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_MASK_OFFMSI_CTRL_INT_6_MASK_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr463660x174R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_6_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr46365MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_6_STATUS_OFFMSI_CTRL_INT_6_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr463840x178R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_6_STATUSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr46383MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_EN_OFFMSI_CTRL_INT_7_EN_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr464010x17CR/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFFIntegrated MSI Reception Module Interrupt#i Enable Register.falsefalsefalsefalseMSI_CTRL_INT_7_ENDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr46400MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_MASK_OFFMSI_CTRL_INT_7_MASK_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr464190x180R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFFIntegrated MSI Reception Module Interrupt#i Mask Register.falsefalsefalsefalseMSI_CTRL_INT_7_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_SETDWC_pcie_wire_cpcie_usp_4x8.csr46418MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI Interrupt Vector.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSI_CTRL_INT_7_STATUS_OFFMSI_CTRL_INT_7_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr464370x184R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFFIntegrated MSI Reception Module Interrupt#i Status Register.falsefalsefalsefalseMSI_CTRL_INT_7_STATUSDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_SETDWC_pcie_wire_cpcie_usp_4x8.csr46436MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.3100x00000000R/W1CregisterDBI_Slave.PF0_PORT_LOGIC.MSI_GPIO_IO_OFFMSI_GPIO_IO_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr464510x188R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSI_GPIO_IO_OFFIntegrated MSI Reception Module General Purpose IO Register.falsefalsefalsefalseMSI_GPIO_REGDBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_GETDBI_SLAVE_PF0_PORT_LOGIC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_SETDWC_pcie_wire_cpcie_usp_4x8.csr46450MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0]Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.CLOCK_GATING_CTRL_OFFCLOCK_GATING_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr465190x18CR/W0x00000003DBI_Slave_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFFThis register enables you to disable dynamic clock gating. By default dynamic clock gating is on, allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module, DWC_pcie_clk_rst.v, and is initiated by the controllers clock enable signals. The following modules support dynamic clock gating: - AXI Bridge - RADMfalsefalsefalsefalseRADM_CLK_GATING_ENDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr46483RADM Clock Gating Enable. This register, if set, enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock, radm_clk_g, to the RADM and is enabled when the controllers clock enable signal, en_radm_clk_g, is asserted. The RADM clock is a gated version of the controller clock, core_clk. The controller de-asserts en_radm_clk_g when there is no Rx traffic, Rx queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR actions pending. - 0: Disable - 1: Enable (default)Note: This register field is sticky.000x1R/WAXI_CLK_GATING_ENDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr46510AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock, the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock, mstr_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, mstr_aclk_active, is asserted. For the AXI Slave this module provides the gated clock, slv_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, slv_aclk_active, is asserted. If the AXI DBI Slave is enabled (DBI_4SLAVE_POPULATED=1) the module provides the gated clock, dbi_axi_aclk_gated, to the AXI Bridge and is enabled when the controllers clock enable signal, dbi_aclk_active, is asserted. The controller de-asserts the clock enable signals when the respective AXI Master/Slave interfaces are idle. - 0: Disable - 1: Enable (default)Note: This register field is sticky.110x1R/WRSVDP_2DBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_MSBDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_LSBDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_RANGEDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_RESETDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_GETDBI_SLAVE_PF0_PORT_LOGIC_CLOCK_GATING_CTRL_OFF_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr46518Reserved for future use.3120x00000000RregisterDBI_Slave.PF0_PORT_LOGIC.GEN3_RELATED_OFFGEN3_RELATED_OFFDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr468640x190R/W0x00402001DBI_Slave_PF0_PORT_LOGIC_GEN3_RELATED_OFFGen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific "Directed Speed Change" field. The "Directed Speed Change" field in the "Link Width and Speed Change Control Register" is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the "Directed Speed Change" field is set to "1" and (2) the "Target Link Speed" field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training.M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.falsefalsefalsefalseGEN3_ZRXDC_NONCOMPLDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_SETDWC_pcie_wire_cpcie_usp_4x8.csr46554Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled. - 0: The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. - 1: The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rates.Note: This register field is sticky.000x1R/WRSVDP_1DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr46562Reserved for future use.710x00RDISABLE_SCRAMBLER_GEN_3DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr46577Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY).Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.880x0R/WEQ_PHASE_2_3DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_PHASE_2_3_SETDWC_pcie_wire_cpcie_usp_4x8.csr46598Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.990x0R/WEQ_EIEOS_CNTDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_SETDWC_pcie_wire_cpcie_usp_4x8.csr46612Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.10100x0R/WEQ_REDODBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_EQ_REDO_SETDWC_pcie_wire_cpcie_usp_4x8.csr46632Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is infinite or you do not want eq requests and redo, setting this bit to 1 will stop the EQ requests and EQ redo so that the link can go ahead to L0 state for packet trasmissions.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.11110x0R/WRXEQ_PH01_ENDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_PH01_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr46663Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY. This bit is used during Virtex-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: - 00: Tx equalization only in phase 2/3 - 01: No Tx equalization, no Rx equalization - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/1 - 11: No Tx equalization, Rx equalization in phase 0/1Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.12120x0R/WRXEQ_RGRDLESS_RXTSDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_SETDWC_pcie_wire_cpcie_usp_4x8.csr46689When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.13130x1R/WRSVDP_14DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr46697Reserved for future use.15140x0RGEN3_EQUALIZATION_DISABLEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr46711Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.16160x0R/WGEN3_DLLP_XMT_DELAY_DISABLEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr46725DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.17170x0R/WGEN3_DC_BALANCE_DISABLEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr46737DC Balance Disable. Disable DC Balance feature.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.18180x0R/WRSVDP_19DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_19_SETDWC_pcie_wire_cpcie_usp_4x8.csr46745Reserved for future use.20190x0RAUTO_EQ_DISABLEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_AUTO_EQ_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr46772Autonomous Equalization Disable. When the controller is in L0 state at Gen3 data rate and equalization was completed successfully in Autonomous EQ Mechanism, setting this bit in DSP will not direct the controller to Recovery state to perform Gen4 equalization. Link stays in Gen3 rate and DSP sends DLLPs to USP. If the bit is 0, DSP will block DLLPs and direct the link to perform Gen4 EQ in Autonomous Mechanism.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.21210x0R/WUSP_SEND_8GT_EQ_TS2_DISABLEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_USP_SEND_8GT_EQ_TS2_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr46799Upstream Port Send 8GT/s or 16GT/s EQ TS2 Disable. The base spec defines that USP can optionally send 8GT or 16GT EQ TS2 and it means USP can set DSP TxPreset value in Gen4 or Gen5 Data Rate. If this register set to 0, USP sends 8GT or 16GT EQ TS2. If this register set to 1, USP does not send 8GT or 16GT EQ TS2. This applies to upstream ports only. No Function for downstream ports.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate. Value after reset in Gen4/Gen5 is 0x1.Note: The access attributes of this field are as follows: - Wire: see description - Dbi: see description Note: This register field is sticky.22220x1R/WGEN3_EQ_INVREQ_EVAL_DIFF_DISABLEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr46814Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shared for Gen3 and Gen4/Gen5 data rate.Note: This register field is sticky.23230x0R/WRATE_SHADOW_SELDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RATE_SHADOW_SEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr46855Rate Shadow Select. This register value decide the Data Rate of shadow register. - 00b: Gen3 Data Rate is selected for shadow register. - 01b: Gen4 Data Rate is selected for shadow register. - 10b: Gen5 Data Rate is selected for shadow register. - 11b: Reserved.The following shadow registers are controlled by this register. - GEN3_RELATED_OFF[9] EQ_PHASE_2_3 - GEN3_RELATED_OFF[12] RXEQ_PH01_EN - GEN3_RELATED_OFF[19] RE_EQ_REQUEST_ENABLE - GEN3_RELATED_OFF[21] AUTO_EQ_DISABLE - GEN3_RELATED_OFF[22] USP_SEND_8GT_EQ_TS2_DISABLE - GEN3_EQ_LOCAL_FS_LF_OFF[5:0] GEN3_EQ_LOCAL_LF - GEN3_EQ_LOCAL_FS_LF_OFF[11:6] GEN3_EQ_LOCAL_FS - GEN3_EQ_PSET_COEFF_MAP_0[5:0] GEN3_EQ_PRE_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[11:6] GEN3_EQ_CURSOR_PSET - GEN3_EQ_PSET_COEFF_MAP_0[17:12] GEN3_EQ_POSET_CURSOR_PSET - GEN3_EQ_CONTROL_OFF[3:0] GEN3_EQ_FB_MODE - GEN3_EQ_CONTROL_OFF[4] GEN3_EQ_PHASE23_EXIT_MODE - GEN3_EQ_CONTROL_OFF[5] GEN3_EQ_EVAL_2MS_DISABLE - GEN3_EQ_CONTROL_OFF[23:8] GEN3_EQ_PSET_REQ_VEC - GEN3_EQ_CONTROL_OFF[24] GEN3_EQ_FOM_INC_INITIAL_EVAL - GEN3_EQ_CONTROL_OFF[25] GEN3_EQ_PSET_REQ_AS_COEF - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[4:0] GEN3_EQ_FMDC_T_MIN_PHASE23 - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[9:5] GEN3_EQ_FMDC_N_EVALS - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[13:10] GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA - GEN3_EQ_FB_MODE_DIR_CHANGE_OFF[17:14] GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTANote: This register field is sticky.25240x0R/WRSVDP_26DBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_RELATED_OFF_RSVDP_26_SETDWC_pcie_wire_cpcie_usp_4x8.csr46863Reserved for future use.31260x00RregisterDBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_CONTROL_OFFGEN3_EQ_CONTROL_OFFDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr470960x1A8R/W0x05039f71DBI_Slave_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFFGen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP).M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist.falsefalsefalsefalseGEN3_EQ_FB_MODEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr46892Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: ReservedNote: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.300x1R/WGEN3_EQ_PHASE23_EXIT_MODEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr46939Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 2 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 2 Complete status bit is set in the "Link Status Register 2"For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.RcvrLockWhen optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 0 - Equalization Phase 3 Successful status bit is set in the "Link Status Register 2" when GEN3_EQ_PHASE23_EXIT_MODE = 1 - Equalization Phase 3 Complete status bit is set in the "Link Status Register 2"Note: GEN3_EQ_PHASE23_EXIT_MODE = 1 affects Direction Change feed back mode. EQ requests for Figure Of Merit mode complete before 24 ms timeout. Please see GEN3_EQ_PSET_REQ_VEC Register for more.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.440x1R/WGEN3_EQ_EVAL_2MS_DISABLEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr46963Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout - 1: ignore the 2ms timeout and continue as normal. This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.550x1R/WGEN3_LOWER_RATE_EQ_REDO_ENABLEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr46977Support EQ redo and lower rate change: - 0: not support - 1: supportNote: Gen3 and Gen4 share the same register bit and have the same feature.Note: This register field is sticky.660x1R/WRSVDP_7DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr46985Reserved for future use.770x0RGEN3_EQ_PSET_REQ_VECDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_SETDWC_pcie_wire_cpcie_usp_4x8.csr47040Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase. - 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: Preset 0 is requested and evaluated in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase - 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase - 000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase - All other encodings: ReservedNote: You must contact your PHY vendor to ensure 24 ms timeout does not occur in presets requests in EQ master phase, i.e., you must set a proper value to the GEN3_EQ_PSET_REQ_VEC register so that the EQ tunning for Figure of Merit in the EQ master phase completes before 24 ms timeout.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.2380x039fR/WGEN3_EQ_FOM_INC_INITIAL_EVALDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_SETDWC_pcie_wire_cpcie_usp_4x8.csr47060Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: IncludeNote: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.24240x1R/WGEN3_EQ_PSET_REQ_AS_COEFDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_SETDWC_pcie_wire_cpcie_usp_4x8.csr47071GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use.Note: This register field is sticky.25250x0R/WGEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAPDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr47087Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: requestNote: Gen3 and Gen4 share the same register bit and have the same feature.Note: This register field is sticky.26260x1R/WRSVDP_27DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr47095Reserved for future use.31270x00RregisterDBI_Slave.PF0_PORT_LOGIC.GEN3_EQ_FB_MODE_DIR_CHANGE_OFFGEN3_EQ_FB_MODE_DIR_CHANGE_OFFDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr472020x1ACR/W0x00000040DBI_Slave_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFFGen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feedback Mode in "Gen3 EQ Control Register" to "Direction Change." These fields allow control over the initial starting point for the search of optimal coefficient settings, and allow control over the criteria used to determine when the optimal settings have been achieved. The values are applied to all the lanes.falsefalsefalsefalseGEN3_EQ_FMDC_T_MIN_PHASE23DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_SETDWC_pcie_wire_cpcie_usp_4x8.csr47127Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time, before starting to check for convergence of the coefficients.Allowed values 0,1,...,24.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.400x00R/WGEN3_EQ_FMDC_N_EVALSDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_SETDWC_pcie_wire_cpcie_usp_4x8.csr47154Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found.Allowed range: 0,1,2,..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH.When set to 0, EQ Master is performed without sending any requests to the remote partner in Phase 2 for USP and Phase 3 for DSP. Therefore, the remote partner will not change its transmitter coefficients and will move to the next state.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.950x02R/WGEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTADBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_SETDWC_pcie_wire_cpcie_usp_4x8.csr47174Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth.Allowed range: 0,1,2,..15.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.13100x0R/WGEN3_EQ_FMDC_MAX_POST_CUSROR_DELTADBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_SETDWC_pcie_wire_cpcie_usp_4x8.csr47193Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15.Note: When CX_GEN4_SPEED/CX_GEN5_SPEED, this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. If RATE_SHADOW_SEL==10b, this register is for Gen5 data rate.Note: This register field is sticky.17140x0R/WRSVDP_18DBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_RSVDP_18_SETDWC_pcie_wire_cpcie_usp_4x8.csr47201Reserved for future use.31180x0000RregisterDBI_Slave.PF0_PORT_LOGIC.ORDER_RULE_CTRL_OFFORDER_RULE_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr472360x1B4R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFFOrder Rule Control Register.falsefalsefalsefalseNP_PASS_PDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_MSBDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_LSBDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_RANGEDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_RESETDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_GETDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_NP_PASS_P_SETDWC_pcie_wire_cpcie_usp_4x8.csr47216Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P700x00R/WCPL_PASS_PDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MSBDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_LSBDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_RANGEDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_RESETDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_GETDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SETDWC_pcie_wire_cpcie_usp_4x8.csr47227Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P1580x00R/WRSVDP_16DBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_MSBDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_LSBDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_RANGEDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_RESETDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_GETDBI_SLAVE_PF0_PORT_LOGIC_ORDER_RULE_CTRL_OFF_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr47235Reserved for future use.31160x0000RregisterDBI_Slave.PF0_PORT_LOGIC.PIPE_LOOPBACK_CONTROL_OFFPIPE_LOOPBACK_CONTROL_OFFDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr472920x1B8R/W0x000000ffDBI_Slave_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFFPIPE Loopback Control Register.falsefalsefalsefalseLPBK_RXVALIDDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_LSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_RESETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_GETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SETDWC_pcie_wire_cpcie_usp_4x8.csr47248LPBK_RXVALID is an internally reserved field. Do not use.Note: This register field is sticky.1500x00ffR/WRXSTATUS_LANEDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_GETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SETDWC_pcie_wire_cpcie_usp_4x8.csr47257RXSTATUS_LANE is an internally reserved field. Do not use.Note: This register field is sticky.21160x00R/WRSVDP_22DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_MSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_LSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_RESETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_GETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr47265Reserved for future use.23220x0RRXSTATUS_VALUEDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_GETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr47274RXSTATUS_VALUE is an internally reserved field. Do not use.2624WRSVDP_27DBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_MSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_LSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_RESETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_GETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_SETDWC_pcie_wire_cpcie_usp_4x8.csr47282Reserved for future use.30270x0RPIPE_LOOPBACKDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_LSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_RESETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_GETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SETDWC_pcie_wire_cpcie_usp_4x8.csr47291PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe.Note: This register field is sticky.31310x0R/WregisterDBI_Slave.PF0_PORT_LOGIC.MISC_CONTROL_1_OFFMISC_CONTROL_1_OFFDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr474860x1BCR/W0x0007ff48DBI_Slave_PF0_PORT_LOGIC_MISC_CONTROL_1_OFFDBI Read-Only Write Enable Register.falsefalsefalsefalseDBI_RO_WR_ENDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr47310Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'.For more details, see "Writing to Read-Only Registers" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.Note: This register field is sticky.000x0R/WDEFAULT_TARGETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_LSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_RESETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_GETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SETDWC_pcie_wire_cpcie_usp_4x8.csr47331Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion with UR status is generated for non-posted requests. - 1: The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application.For more details, see "ECRC Handling" and "Request TLP Routing Rules" in "Receive Routing" section of the "Controller Operations" chapter of the Databook.Note: This register field is sticky.110x0R/WUR_CA_MASK_4_TRGT1DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_LSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_RESETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_GETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SETDWC_pcie_wire_cpcie_usp_4x8.csr47345When this field is set to '1', the controller suppresses error logging, error message generation, and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is, when DEFAULT_TARGET =1). For more details, see "Advanced Error Handling For Received TLPs" chapter of the Databook.Note: This register field is sticky.220x0R/WSIMPLIFIED_REPLAY_TIMERDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_LSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_RESETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_GETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SETDWC_pcie_wire_cpcie_usp_4x8.csr47364Enables Simplified Replay Timer (Gen4). For more details, see "Transmit Replay" in "Transmit TLP Processing" section in the "Controller Operations" chapter of the Databook.Simplified Replay Timer can have the following Values: - A value from 24,000 to 31,000 Symbol Times when Extended Synch is 0b. - A value from 80,000 to 100,000 Symbol Times when Extended Synch is 1b.The Simplified Replay Timer value must not be changed while the link is in use.Note: This register field is sticky.330x1R/WDISABLE_AUTO_LTR_CLR_MSGDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_MSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_LSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_RESETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_GETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_SETDWC_pcie_wire_cpcie_usp_4x8.csr47382Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear message.For more details, see "Latency Tolerance Reporting (LTR) Message Generation[EP Mode]" in "Message Generation" section of the "Controller Operations" chapter of the Databook.Note: This register field is sticky.440x0R/WARI_DEVICE_NUMBERDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_LSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_RESETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_GETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr47392When ARI is enabled, this field enables use of the device ID.Note: This register field is sticky.550x0R/WCPLQ_MNG_ENDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr47402This field enables the Completion Queue Management feature.Note: This register field is sticky.660x1R/WCFG_TLP_BYPASS_EN_REGDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_MSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_LSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_RESETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_GETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_SETDWC_pcie_wire_cpcie_usp_4x8.csr47421Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to the setting of TARGET_ABOVE_CONFIG_LIMIT_REG - 1: Configuration TLPs are routed according to the setting of CONFIG_LIMIT_REGNote: When app_req_retry_en is asserted, the setting of this field is ignored.Note: This register field is sticky.770x0R/WCONFIG_LIMIT_REGDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_MSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_LSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_RESETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_GETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_SETDWC_pcie_wire_cpcie_usp_4x8.csr47442Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of TARGET_ABOVE_CONFIG_LIMIT_REG field.Your application must set a proper value for this field based on your extended configuration registers. For more details, see the "CDM/ELBI Register Space Access Through CFG Request" in "Register Module, LBC, and DBI" section in the "Controller Operations" chapter of the Databook.Note: This register field is sticky.1780x3ffR/WTARGET_ABOVE_CONFIG_LIMIT_REGDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_MSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_LSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_RESETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_GETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_SETDWC_pcie_wire_cpcie_usp_4x8.csr47455Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1Note: This register field is sticky.19180x1R/WP2P_TRACK_CPL_TO_REGDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_MSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_LSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_RESETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_GETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_SETDWC_pcie_wire_cpcie_usp_4x8.csr47466Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reportingNote: This register field is sticky.20200x0R/WP2P_ERR_RPT_CTRLDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_MSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_LSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_RESETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_GETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_SETDWC_pcie_wire_cpcie_usp_4x8.csr47477Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completionNote: This register field is sticky.21210x0R/WRSVDP_22DBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_MSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_LSBDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_RESETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_GETDBI_SLAVE_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_RSVDP_22_SETDWC_pcie_wire_cpcie_usp_4x8.csr47485Reserved for future use.31220x000RregisterDBI_Slave.PF0_PORT_LOGIC.MULTI_LANE_CONTROL_OFFMULTI_LANE_CONTROL_OFFDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr475600x1C0R/W0x00000080DBI_Slave_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFFUpConfigure Multi-lane Control Register.Used when upsizing or downsizing the link width through Configuration state without bringing the link down.For more details, see the "Link Establishment" section in the "ControllerOperations" chapter of the Databook.falsefalsefalsefalseTARGET_LINK_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MSBDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_LSBDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_RESETDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_GETDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr47513Target Link Width.Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 - 6'b100000: x32This field is reserved (fixed to '0') for M-PCIe.500x00R/WDIRECT_LINK_WIDTH_CHANGEDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MSBDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_LSBDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_RESETDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_GETDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SETDWC_pcie_wire_cpcie_usp_4x8.csr47536Directed Link Width Change.The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the controller starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the controller does not start upconfigure or autonomous width downsizing in the Configuration state.The controller self-clears this field when the controller accepts this request.This field is reserved (fixed to '0') for M-PCIe.660x0R/WUPCONFIGURE_SUPPORTDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MSBDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_LSBDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_RESETDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_GETDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SETDWC_pcie_wire_cpcie_usp_4x8.csr47551Upconfigure Support.The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state.This field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.770x1R/WRSVDP_8DBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_MSBDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_LSBDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_RESETDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_GETDBI_SLAVE_PF0_PORT_LOGIC_MULTI_LANE_CONTROL_OFF_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr47559Reserved for future use.3180x000000RregisterDBI_Slave.PF0_PORT_LOGIC.PHY_INTEROP_CTRL_OFFPHY_INTEROP_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr476760x1C4R/W0x00000a44DBI_Slave_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFFPHY Interoperability Control Register.falsefalsefalsefalseRXSTANDBY_CONTROLDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_LSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_RESETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_GETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SETDWC_pcie_wire_cpcie_usp_4x8.csr47589Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP2 - [4]: RxL0s.Idle - [5]: EI Infer in L0 - [6]: Execute RxStandby/RxStandbyStatus HandshakeThis field is reserved (fixed to '0') for M-PCIe.Note: This register field is sticky.600x44R/WRSVDP_7DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_MSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_LSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_RESETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_GETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr47597Reserved for future use.770x0RL1SUB_EXIT_MODEDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr47614L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for the PHY to assert phy_mac_pclkack_n. - 0: Controller waits for the PHY to assert phy_mac_pclkack_n before exiting L1.Note: This register field is sticky.880x0R/WL1_NOWAIT_P1DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_LSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_RESETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_GETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SETDWC_pcie_wire_cpcie_usp_4x8.csr47635L1 entry control bit. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Controller waits for the PHY to acknowledge transition to P1 before entering L1.Note: The access attributes of this field are as follows: - Wire: R/W (sticky) - Dbi: R/W (sticky) Note: This register field is sticky.990x1RL1_CLK_SELDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_LSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_RESETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_GETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr47652L1 Clock control bit. This field is reserved for internal use.You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in L1. - 0: Controller requests aux_clk switch and core_clk gating in L1.Note: This register field is sticky.10100x0R/WP2NOBEACON_ENABLEDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_P2NOBEACON_ENABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr47667P2.NoBeacon Enable bit. - 1: Controller drives P2.NoBeacon encoding for PHY power down state, when the link goes to L2. - 0: Controller drives P2 encoding for PHY power down state, when the link goes to L2.Note:This field is reserved (fixed to '0') if CX_P2NOBEACON_ENABLE is not set.Note: This register field is sticky.11110x1R/WRSVDP_12DBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_MSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_LSBDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_RESETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_GETDBI_SLAVE_PF0_PORT_LOGIC_PHY_INTEROP_CTRL_OFF_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr47675Reserved for future use.31120x00000RregisterDBI_Slave.PF0_PORT_LOGIC.TRGT_CPL_LUT_DELETE_ENTRY_OFFTRGT_CPL_LUT_DELETE_ENTRY_OFFDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr477120x1C8R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFFTRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion because of an FLR or any other reason.Note:: The target completion LUT (and associated target completion timeout event) is watching for completions (from your application on XALI0/1/2 or AXI master read channel) corresponding to previously received non-posted requests from the PCIe wire.falsefalsefalsefalseLOOK_UP_IDDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_LSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_RESETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_GETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SETDWC_pcie_wire_cpcie_usp_4x8.csr47698This number selects one entry to delete of the TRGT_CPL_LUT.3000x00000000R/WDELETE_ENDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr47711This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field.This is a self-clearing register field. Reading from this register field always returns a '0'.31310x0WregisterDBI_Slave.PF0_PORT_LOGIC.LINK_FLUSH_CONTROL_OFFLINK_FLUSH_CONTROL_OFFDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr477580x1CCR/W0xff000001DBI_Slave_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFFLink Reset Request Flush Control Register.falsefalsefalsefalseAUTO_FLUSH_ENDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr47740Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge.The flushing process is initiated if any of the following events occur: - Hot reset request. A downstream port (DSP) can "hot reset" an upstream port (USP) by sending two consecutive TS1 ordered sets with the hot reset bit asserted. - Warm (Soft) reset request. Generated when exiting from D3 to D0 and cfg_pm_no_soft_rst=0. - Link down reset request. A high to low transition on smlh_req_rst_not indicates the link has gone down and the controller is requesting a reset.If you disable automatic flushing, your application is responsible for resetting the PCIe controller and the AXI Bridge. For more details see "Warm and Hot Resets" section in the Architecture chapter of the Databook.Note: This register field is sticky.000x1R/WRSVDP_1DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_MSBDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_LSBDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_RESETDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_GETDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr47748Reserved for future use.2310x000000RRSVD_I_8DBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_MSBDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_LSBDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_RANGEDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_RESETDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_GETDBI_SLAVE_PF0_PORT_LOGIC_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr47757This is an internally reserved field. Do not use.Note: This register field is sticky.31240xffR/WregisterDBI_Slave.PF0_PORT_LOGIC.AMBA_ERROR_RESPONSE_DEFAULT_OFFAMBA_ERROR_RESPONSE_DEFAULT_OFFDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr47888AXI Bridge Slave Error Response Register.0x1D0R/W0x00009c00DBI_Slave_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFFAXI Bridge Slave Error Response Register.falsefalsefalsefalseAMBA_ERROR_RESPONSE_GLOBALDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SETDWC_pcie_wire_cpcie_usp_4x8.csr47787Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - 0: OKAY (with FFFF data for non-posted requests) and ignore the setting in bit [2] of this register. - 1: ERROR for normal link (data) accesses and look at bit [2] for other scenarios.AXI: - 0: OKAY (with FFFF data for non-posted requests) - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)The error response mapping is not applicable to Non-existent Vendor ID register reads.Note: This register field is sticky.000x0R/WRSVDP_1DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr47795Reserved for future use.110x0RAMBA_ERROR_RESPONSE_VENDORIDDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SETDWC_pcie_wire_cpcie_usp_4x8.csr47814Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - 0: OKAY (with FFFF data). The controller ignores the setting in the bit when bit 0 of this register is '0'. - 1: ERRORAXI: - 0: OKAY (with FFFF data). - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)Note: This register field is sticky.220x0R/WAMBA_ERROR_RESPONSE_CRSDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SETDWC_pcie_wire_cpcie_usp_4x8.csr47836CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see "Error Handling" in the AXI chapter of the Databook.AHB: - always returns OKAYAXI: - 00: OKAY - 01: OKAY with all FFFF_FFFF data for all CRS completions - 10: OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with FFFF_FFFF data for all other CRS completions - 11: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping)Note: This register field is sticky.430x0R/WRSVDP_5DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr47844Reserved for future use.950x00RAMBA_ERROR_RESPONSE_MAPDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SETDWC_pcie_wire_cpcie_usp_4x8.csr47879AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses, slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is always mapped to OKAY. - [0] -- 0: UR (unsupported request) -> DECERR -- 1: UR (unsupported request) -> SLVERR - [1] -- 0: CRS (configuration retry status) -> DECERR -- 1: CRS (configuration retry status) -> SLVERR - [2] -- 0: CA (completer abort) -> DECERR -- 1: CA (completer abort) -> SLVERR - [3]: Reserved - [4]: Reserved - [5]: -- 0: Completion Timeout -> DECERR -- 1: Completion Timeout -> SLVERRThe AXI bridge internally drops (processes internally but not passed to your application) a completion that has been marked by the Rx filter as UC or MLF, and does not pass its status directly down to the slave interface. It waits for a timeout and then signals "Completion Timeout" to the slave interface.The controller sets the AXI slave read databus to 0xFFFF for all error responses.Note: This register field is sticky.15100x27R/WRSVDP_16DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_SETDWC_pcie_wire_cpcie_usp_4x8.csr47887Reserved for future use.31160x0000RregisterDBI_Slave.PF0_PORT_LOGIC.AMBA_LINK_TIMEOUT_OFFAMBA_LINK_TIMEOUT_OFFDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr479350x1D4R/W0x00000032DBI_Slave_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFFLink Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational, the controller starts a "flush" timer. The timeout value of the timer is set by this register. If the timer times out before the PCIe link is operational, the bridge TX request queues are flushed. For more details, see the "AXI Bridge Initialization, Clocking and Reset" section in the AXI chapter of the Databook.falsefalsefalsefalseLINK_TIMEOUT_PERIOD_DEFAULTDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SETDWC_pcie_wire_cpcie_usp_4x8.csr47916Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not transmitting any of these requests.The timer is clocked by core_clk. For an M-PCIe configuration: - Time unit of this field is 4 ms. - Margin of error for RateA clock is < 1%. - Margin of error for RateB clock is between 16% and 17%.Note: This register field is sticky.700x32R/WLINK_TIMEOUT_ENABLE_DEFAULTDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SETDWC_pcie_wire_cpcie_usp_4x8.csr47926Disable Flush. You can disable the flush feature by setting this field to "1".Note: This register field is sticky.880x0R/WRSVDP_9DBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr47934Reserved for future use.3190x000000RregisterDBI_Slave.PF0_PORT_LOGIC.AMBA_ORDERING_CTRL_OFFAMBA_ORDERING_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr480450x1D8R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFFAMBA Ordering Control.falsefalsefalsefalseRSVDP_0DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_0_SETDWC_pcie_wire_cpcie_usp_4x8.csr47946Reserved for future use.000x0RAX_SNP_ENDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr47960AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR and WAW hazards at the remote link partner. For more details, see the "Optional Serialization of AXI Slave Non-posted Requests" section in the AXI chapter of the Databook.110x0R/WRSVDP_2DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr47968Reserved for future use.220x0RAX_MSTR_ORDR_P_EVENT_SELDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SETDWC_pcie_wire_cpcie_usp_4x8.csr48012AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule, "NP must not pass P" at the AXI Master Interface.The AXI protocol does not support ordering between channels. Therefore, NP reads can pass P on your AXI bus fabric. This can result in an ordering violation when the read overtakes a P that is going to the same address. Therefore, the bridge master does not issue any NP requests until all outstanding P writes reach their destination. It does this by waiting for the all of the write responses on the B channel. This can affect the performance of the master read channel.For scenarios where the interconnect serializes the AXI master "AW", "W" and "AR" channels,you can increase the performance by reducing the need to wait until the complete Posted transaction has effectively reached the application slave. - 00: B'last event: wait for the all of the write responses on the B channel thereby ensuring that the complete Posted transaction has effectively reached the application slave (default). - 01: AW'last event: wait until the complete Posted transaction has left the AXI address channel at the bridge master. - 10: W'last event: wait until the complete Posted transaction has left the AXI data channel at the bridge master. - 11: ReservedNote 2: This setting will not affect: - MSI interrupt catcher and P data ordering. This is always driven by the B'last event. - DMA read engine TLP ordering. This is always driven by the B'last event. - NP write transactions which are always serialized with P write transactions.430x0R/WRSVDP_5DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_5_SETDWC_pcie_wire_cpcie_usp_4x8.csr48020Reserved for future use.650x0RAX_MSTR_ZEROLREAD_FWDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SETDWC_pcie_wire_cpcie_usp_4x8.csr48036AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read, implementing the PCIe express flush semantics of the Posted transactions. - 0x0: The zero length Read is terminated at the DW PCIe AXI bridge master - 0x1: The zero length Read is forward to the application.770x0R/WRSVDP_8DBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_MSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_LSBDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_RESETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_GETDBI_SLAVE_PF0_PORT_LOGIC_AMBA_ORDERING_CTRL_OFF_RSVDP_8_SETDWC_pcie_wire_cpcie_usp_4x8.csr48044Reserved for future use.3180x000000RregisterDBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_1_OFFCOHERENCY_CONTROL_1_OFFDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr480820x1E0R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFFACE Cache Coherency Control Register 1falsefalsefalsefalseCFG_MEMTYPE_VALUEDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_MSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_LSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_RESETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_GETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48059Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = PeripheralNote: This register field is sticky.000x0R/WRSVDP_1DBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_MSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_LSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_RESETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_GETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr48067Reserved for future use.110x0RCFG_MEMTYPE_BOUNDARY_LOW_ADDRDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_LSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_RANGEDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_RESETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_GETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_SETDWC_pcie_wire_cpcie_usp_4x8.csr48081Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are "00". Addresses up to but not including this value are in the lower address space region; addresses equal or greater than this value are in the upper address space region.Note: This register field is sticky.3120x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_2_OFFCOHERENCY_CONTROL_2_OFFDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr480970x1E4R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFFACE Cache Coherency Control Register 2falsefalsefalsefalseCFG_MEMTYPE_BOUNDARY_HIGH_ADDRDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_MSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_LSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_RANGEDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_RESETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_GETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_SETDWC_pcie_wire_cpcie_usp_4x8.csr48096Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.COHERENCY_CONTROL_3_OFFCOHERENCY_CONTROL_3_OFFDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr481550x1E8R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFFACE Cache Coherency Control Register 3falsefalsefalsefalse--200x0rCFG_MSTR_ARCACHE_MODEDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48113Master Read CACHE Signal Behavior.Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE fieldNote: This register field is sticky.630x0R/W--1070x0rCFG_MSTR_AWCACHE_MODEDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48129Master Write CACHE Signal Behavior.Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE fieldNote: for message requests the value of mstr_awcache is always "0000" regardless of the value of this bitNote: This register field is sticky.14110x0R/W--18150x0rCFG_MSTR_ARCACHE_VALUEDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_MSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_LSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_RESETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_GETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48140Master Read CACHE Signal Value.Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'.Note: This register field is sticky.22190x0R/W--26230x0rCFG_MSTR_AWCACHE_VALUEDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_MSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_LSBDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_RESETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_GETDBI_SLAVE_PF0_PORT_LOGIC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48154Master Write CACHE Signal Value.Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'.Note: not applicable to message requests; for message requests the value of mstr_awcache is always "0000"Note: This register field is sticky.30270x0R/W--31310x0rregisterDBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_LOW_OFFAXI_MSTR_MSG_ADDR_LOW_OFFDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr481880x1F0R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFFLower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases, the third and fourth DWORDs of a message (Msg/MsgD) TLP header were delivered though the AXI master address bus (mstr_awaddr). These DWORDS are now supplied through the mstr_awmisc_info_hdr_34dw[63:0] output; and the value on mstr_awaddr is driven to the value you have programmed into the AXI_MSTR_MSG_ADDR_LOW_OFF and AXI_MSTR_MSG_ADDR_HIGH_OFF registers.falsefalsefalsefalseCFG_AXIMSTR_MSG_ADDR_LOW_RESERVEDDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MSBDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_LSBDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_RESETDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_GETDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SETDWC_pcie_wire_cpcie_usp_4x8.csr48177Reserved for future use.Note: This register field is sticky.1100x000RCFG_AXIMSTR_MSG_ADDR_LOWDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MSBDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_LSBDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESETDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_GETDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SETDWC_pcie_wire_cpcie_usp_4x8.csr48187Lower 20 bits of the programmable AXI address for Messages.Note: This register field is sticky.31120x00000R/WregisterDBI_Slave.PF0_PORT_LOGIC.AXI_MSTR_MSG_ADDR_HIGH_OFFAXI_MSTR_MSG_ADDR_HIGH_OFFDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr482030x1F4R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFFUpper 32 bits of the programmable AXI address where Messages coming from wire are mapped to.falsefalsefalsefalseCFG_AXIMSTR_MSG_ADDR_HIGHDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MSBDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_LSBDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_RESETDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_GETDBI_SLAVE_PF0_PORT_LOGIC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SETDWC_pcie_wire_cpcie_usp_4x8.csr48202Upper 32 bits of the programmable AXI address for Messages.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_NUMBER_OFFPCIE_VERSION_NUMBER_OFFDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr482280x1F8R0x3533302aDBI_Slave_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFFPCIe Controller IIP Release Version Number. The version number is given inhex format. You should convert each pair of hex characters to ASCII to interpret.Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga**Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01GA is a general release available on www.designware.comEA is an early release available on a per-customer basis.falsefalsefalsefalseVERSION_NUMBERDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MSBDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_LSBDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_RESETDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_GETDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SETDWC_pcie_wire_cpcie_usp_4x8.csr48227Version Number.3100x3533302aRregisterDBI_Slave.PF0_PORT_LOGIC.PCIE_VERSION_TYPE_OFFPCIE_VERSION_TYPE_OFFDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr482530x1FCR0x6c703038DBI_Slave_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFFPCIe Controller IIP Release Version Type. The type is given inhex format. You should convert each pair of hex characters to ASCII to interpret.Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates to ga**Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01GA is a general release available on www.designware.comEA is an early release available on a per-customer basis.falsefalsefalsefalseVERSION_TYPEDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_GETDBI_SLAVE_PF0_PORT_LOGIC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48252Version Type.3100x6c703038RregisterDBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_LOW_OFFMSIX_ADDRESS_MATCH_LOW_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr482950x240R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFFMSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_HIGH_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPsfalsefalsefalsefalseMSIX_ADDRESS_MATCH_ENDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_SETDWC_pcie_wire_cpcie_usp_4x8.csr48275MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present.Note: This register field is sticky.000x0R/WMSIX_ADDRESS_MATCH_RESERVED_1DBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_RESERVED_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr48285Reserved.Note: This register field is sticky.110x0RMSIX_ADDRESS_MATCH_LOWDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_LOW_SETDWC_pcie_wire_cpcie_usp_4x8.csr48294MSI-X Address Match Low Address.Note: This register field is sticky.3120x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSIX_ADDRESS_MATCH_HIGH_OFFMSIX_ADDRESS_MATCH_HIGH_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr483170x244R/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFFMSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. This register is only used in AXI configurations. When your local AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_LOW_OFF), the controller will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPsfalsefalsefalsefalseMSIX_ADDRESS_MATCH_HIGHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_ADDRESS_MATCH_HIGH_OFF_MSIX_ADDRESS_MATCH_HIGH_SETDWC_pcie_wire_cpcie_usp_4x8.csr48316MSI-X Address Match High Address.Note: This register field is sticky.3100x00000000R/WregisterDBI_Slave.PF0_PORT_LOGIC.MSIX_DOORBELL_OFFMSIX_DOORBELL_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr483910x248W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSIX_DOORBELL_OFFMSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook. - For AXI configurations: when your local application writes (MWr) to the address defined in MSIX_ADDRESS_MATCH_LOW_OFF, the controller will load this register with the contents of the MWr and subsequently create and send MSI-X TLPs. - For AHB configurations: the MSI-X Table RAM feature is not supported. - For non-AMBA configurations: when your local application writes to this register, the controller will create and send MSI-X TLPs.falsefalsefalsefalseMSIX_DOORBELL_VECTORDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VECTOR_SETDWC_pcie_wire_cpcie_usp_4x8.csr48342MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for.1000x000WMSIX_DOORBELL_RESERVED_11DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_11_SETDWC_pcie_wire_cpcie_usp_4x8.csr48349Reserved.11110x0WMSIX_DOORBELL_TCDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_TC_SETDWC_pcie_wire_cpcie_usp_4x8.csr48358MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with.14120x0WMSIX_DOORBELL_VF_ACTIVEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_ACTIVE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48367MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction.15150x0WMSIX_DOORBELL_VFDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_VF_SETDWC_pcie_wire_cpcie_usp_4x8.csr48375MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction.23160x00WMSIX_DOORBELL_PFDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_PF_SETDWC_pcie_wire_cpcie_usp_4x8.csr48383MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction.28240x00WMSIX_DOORBELL_RESERVED_29_31DBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_DOORBELL_OFF_MSIX_DOORBELL_RESERVED_29_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr48390Reserved.31290x0WregisterDBI_Slave.PF0_PORT_LOGIC.MSIX_RAM_CTRL_OFFMSIX_RAM_CTRL_OFFDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr485290x24CR/W0x00000000DBI_Slave_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFFMSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to generate MSI-X requests. For more details, see the Interrupts section in the "Controller Operations" chapter of the Databook.falsefalsefalsefalseMSIX_RAM_CTRL_TABLE_DSDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_DS_SETDWC_pcie_wire_cpcie_usp_4x8.csr48409MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode.Note: This register field is sticky.000x0R/WMSIX_RAM_CTRL_TABLE_SDDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_TABLE_SD_SETDWC_pcie_wire_cpcie_usp_4x8.csr48420MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode.Note: This register field is sticky.110x0R/WMSIX_RAM_CTRL_RESERVED_2_7DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_2_7_SETDWC_pcie_wire_cpcie_usp_4x8.csr48430Reserved.Note: This register field is sticky.720x00RMSIX_RAM_CTRL_PBA_DSDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_DS_SETDWC_pcie_wire_cpcie_usp_4x8.csr48441MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode.Note: This register field is sticky.880x0R/WMSIX_RAM_CTRL_PBA_SDDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_PBA_SD_SETDWC_pcie_wire_cpcie_usp_4x8.csr48452MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode.Note: This register field is sticky.990x0R/WMSIX_RAM_CTRL_RESERVED_10_15DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_10_15_SETDWC_pcie_wire_cpcie_usp_4x8.csr48462Reserved.Note: This register field is sticky.15100x00RMSIX_RAM_CTRL_BYPASSDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_BYPASS_SETDWC_pcie_wire_cpcie_usp_4x8.csr48478MSIX RAM Control Bypass. The bypass field, when set, disables the internal generation of low power signals for both RAMs.It is up to the application to ensure the RAMs are in the proper power state before trying to access them. Moreover, the application needs to observe all timing requirements of the RAM low power signals before trying to use the MSIX functionality.Note: This register field is sticky.16160x0R/WMSIX_RAM_CTRL_RESERVED_17_23DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_17_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr48488Reserved.Note: This register field is sticky.23170x00RMSIX_RAM_CTRL_DBG_TABLEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_TABLE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48503MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.Note: This register field is sticky.24240x0R/WMSIX_RAM_CTRL_DBG_PBADBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_DBG_PBA_SETDWC_pcie_wire_cpcie_usp_4x8.csr48518MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of the BAR (indicated by the BIR) in function 0.Note: This register field is sticky.25250x0R/WMSIX_RAM_CTRL_RESERVED_26_31DBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_MSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_LSBDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_RANGEDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_RESETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_GETDBI_SLAVE_PF0_PORT_LOGIC_MSIX_RAM_CTRL_OFF_MSIX_RAM_CTRL_RESERVED_26_31_SETDWC_pcie_wire_cpcie_usp_4x8.csr48528Reserved.Note: This register field is sticky.31260x00RregisterDBI_Slave.PF0_PORT_LOGIC.PL_LTR_LATENCY_OFFPL_LTR_LATENCY_OFFDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr486220x430R0x00000000DBI_Slave_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFFLTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port, the register fields capture the corresponding fields in the LTR messages that are transmitted by the port. For a downstream port, the register fields capture the corresponding fields in the LTR messages that are received by the port. The full content of the register is reflected on the app_ltr_latency[31:0] output.falsefalsefalsefalseSNOOP_LATENCY_VALUEDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_GETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48552Snoop Latency Value.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 900x000RSNOOP_LATENCY_SCALEDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48563Snoop Latency Scale.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 12100x0RRSVDP_13DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_MSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_LSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_RESETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_GETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_13_SETDWC_pcie_wire_cpcie_usp_4x8.csr48570Reserved for future use.14130x0RSNOOP_LATENCY_REQUIREDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_GETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48581Snoop Latency Requirement.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 15150x0RNO_SNOOP_LATENCY_VALUEDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_GETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48592No Snoop Latency Value.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 25160x000RNO_SNOOP_LATENCY_SCALEDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_GETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48603No Snoop Latency Scale.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 28260x0RRSVDP_29DBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_MSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_LSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_RESETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_GETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr48610Reserved for future use.30290x0RNO_SNOOP_LATENCY_REQUIREDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_GETDBI_SLAVE_PF0_PORT_LOGIC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48621No Snoop Latency Requirement.Note: The access attributes of this field are as follows: - Wire: R - Dbi: R/W 31310x0RregisterDBI_Slave.PF0_PORT_LOGIC.AUX_CLK_FREQ_OFFAUX_CLK_FREQ_OFFDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr486570x440R/W0x00000018DBI_Slave_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFFAuxiliary Clock Frequency Control Register.falsefalsefalsefalseAUX_CLK_FREQDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MSBDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_LSBDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_RESETDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_GETDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SETDWC_pcie_wire_cpcie_usp_4x8.csr48648The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk.Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted.If the actual frequency (f) of aux_clk does not exactly match the programmed frequency (f_prog), then there is an error in the time counted by the controller that can be expressed in percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3 MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the controller on aux_clk will be 20% greater than the time in us programmed in the corresponding time register (for example T_POWER_ON).Note: This register field is sticky.900x018R/WRSVDP_10DBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_MSBDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_LSBDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_RANGEDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_RESETDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_GETDBI_SLAVE_PF0_PORT_LOGIC_AUX_CLK_FREQ_OFF_RSVDP_10_SETDWC_pcie_wire_cpcie_usp_4x8.csr48656Reserved for future use.31100x000000RregisterDBI_Slave.PF0_PORT_LOGIC.L1_SUBSTATES_OFFL1_SUBSTATES_OFFDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr487170x444R/W0x000000d2DBI_Slave_PF0_PORT_LOGIC_L1_SUBSTATES_OFFL1 Substates Timing Register.falsefalsefalsefalseL1SUB_T_POWER_OFFDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MSBDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_LSBDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_RANGEDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_RESETDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_GETDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SETDWC_pcie_wire_cpcie_usp_4x8.csr48670Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3.Note: This register field is sticky.100x2R/WL1SUB_T_L1_2DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MSBDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_LSBDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_RANGEDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_RESETDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_GETDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SETDWC_pcie_wire_cpcie_usp_4x8.csr48680Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15.Note: This register field is sticky.520x4R/WL1SUB_T_PCLKACKDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_MSBDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LSBDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_RANGEDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_RESETDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_GETDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_SETDWC_pcie_wire_cpcie_usp_4x8.csr48693Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be L1SUB_T_PCLKACK + 1. Range is 0..3Note: This register field is sticky.760x3R/WL1SUB_LOW_POWER_CLOCK_SWITCH_MODEDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48708If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the controller will delay the switching of aux_clk to the slow platform clock until it detects that the link partner has de-asserted CLKREQ#.Note: This register field is sticky.880x0R/WRSVDP_9DBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_MSBDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_LSBDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_RANGEDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_RESETDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_GETDBI_SLAVE_PF0_PORT_LOGIC_L1_SUBSTATES_OFF_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr48716Reserved for future use.3190x000000RregisterDBI_Slave.PF0_PORT_LOGIC.POWERDOWN_CTRL_STATUS_OFFPOWERDOWN_CTRL_STATUS_OFFDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr487780x448R/W0x00000220DBI_Slave_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFFPowerdown Control and Status Register.falsefalsefalsefalsePOWERDOWN_FORCEDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_MSBDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_LSBDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_RESETDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_GETDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48736This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event that the P2 Powerdown transition does not complete. It will allow the controller to proceed with the transition to the P1 Powerdown state. This field always reads back as 1'b0.000x0WRSVDP_1DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_MSBDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_LSBDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_RANGEDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_RESETDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_GETDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_1_SETDWC_pcie_wire_cpcie_usp_4x8.csr48744Reserved for future use.310x0RPOWERDOWN_MAC_POWERDOWNDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_MSBDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_LSBDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_RESETDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_GETDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_SETDWC_pcie_wire_cpcie_usp_4x8.csr48755This field represents the Powerdown value driven by the controller to the PHY.740x2RPOWERDOWN_PHY_POWERDOWNDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_MSBDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_LSBDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_RANGEDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_RESETDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_GETDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_SETDWC_pcie_wire_cpcie_usp_4x8.csr48769This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller, when the PHY has returned the Phystatus acknowledgment for the Powerdown transition.1180x2RRSVDP_12DBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_MSBDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_LSBDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_RANGEDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_RESETDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_GETDBI_SLAVE_PF0_PORT_LOGIC_POWERDOWN_CTRL_STATUS_OFF_RSVDP_12_SETDWC_pcie_wire_cpcie_usp_4x8.csr48777Reserved for future use.31120x00000RregisterDBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_1_OFFGEN4_LANE_MARGINING_1_OFFDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr488660x480R/W0x05201409DBI_Slave_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFFGen4 Lane Margining 1 Register.falsefalsefalsefalseMARGINING_NUM_TIMING_STEPSDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_TIMING_STEPS_SETDWC_pcie_wire_cpcie_usp_4x8.csr48794M(NumTimingSteps) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.500x09R/WRSVDP_6DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr48802Reserved for future use.760x0RMARGINING_MAX_TIMING_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_TIMING_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr48815M(MaxTimingOffset) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.1380x14R/WRSVDP_14DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr48823Reserved for future use.15140x0RMARGINING_NUM_VOLTAGE_STEPSDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_NUM_VOLTAGE_STEPS_SETDWC_pcie_wire_cpcie_usp_4x8.csr48836M(NumVoltageSteps) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.22160x20R/WRSVDP_23DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_23_SETDWC_pcie_wire_cpcie_usp_4x8.csr48844Reserved for future use.23230x0RMARGINING_MAX_VOLTAGE_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_MARGINING_MAX_VOLTAGE_OFFSET_SETDWC_pcie_wire_cpcie_usp_4x8.csr48857M(MaxVoltageOffset) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.29240x05R/WRSVDP_30DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_1_OFF_RSVDP_30_SETDWC_pcie_wire_cpcie_usp_4x8.csr48865Reserved for future use.31300x0RregisterDBI_Slave.PF0_PORT_LOGIC.GEN4_LANE_MARGINING_2_OFFGEN4_LANE_MARGINING_2_OFFDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr490130x484R/W0x060f0000DBI_Slave_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFFGen4 Lane Margining 2 Register.falsefalsefalsefalseMARGINING_SAMPLE_RATE_VOLTAGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_VOLTAGE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48885M(SamplingRateVoltage) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The M(SamplingRateVoltage) is fixed to 63 internally.Note: This register field is sticky.500x00R/WRSVDP_6DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_6_SETDWC_pcie_wire_cpcie_usp_4x8.csr48893Reserved for future use.760x0RMARGINING_SAMPLE_RATE_TIMINGDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_RATE_TIMING_SETDWC_pcie_wire_cpcie_usp_4x8.csr48909M(SamplingRateTiming) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter , see the PCI Express Base Specification 4.0.Note: This value is not used when MARGINING_IND_ERROR_SAMPLER is 0b. The M(SamplingRateTiming) is fixed to 63 internally.Note: This register field is sticky.1380x00R/WRSVDP_14DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_14_SETDWC_pcie_wire_cpcie_usp_4x8.csr48917Reserved for future use.15140x0RMARGINING_MAXLANESDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_MAXLANES_SETDWC_pcie_wire_cpcie_usp_4x8.csr48930M(MaxLanes) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.20160x0fR/WRSVDP_21DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_21_SETDWC_pcie_wire_cpcie_usp_4x8.csr48938Reserved for future use.23210x0RMARGINING_VOLTAGE_SUPPORTEDDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_VOLTAGE_SUPPORTED_SETDWC_pcie_wire_cpcie_usp_4x8.csr48951M(VoltageSupported) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.24240x0R/WMARGINING_IND_UP_DOWN_VOLTAGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_UP_DOWN_VOLTAGE_SETDWC_pcie_wire_cpcie_usp_4x8.csr48964M(IndUpDownVoltage) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.25250x1R/WMARGINING_IND_LEFT_RIGHT_TIMINGDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_LEFT_RIGHT_TIMING_SETDWC_pcie_wire_cpcie_usp_4x8.csr48977M(IndLeftRightTiming) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.26260x1R/WMARGINING_SAMPLE_REPORTING_METHODDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_SAMPLE_REPORTING_METHOD_SETDWC_pcie_wire_cpcie_usp_4x8.csr48991M(SampleReportingMethod) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.27270x0R/WMARGINING_IND_ERROR_SAMPLERDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_MARGINING_IND_ERROR_SAMPLER_SETDWC_pcie_wire_cpcie_usp_4x8.csr49004M(IndErrorSampler) for Lane Margining at the Receiver.This parameter is defined in 9 Electrical Sub-Block of PCI Express Base Specification 4.0.For a description of this standard PCIe parameter, see the PCI Express Base Specification 4.0.Note: This register field is sticky.28280x0R/WRSVDP_29DBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_MSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_LSBDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_RANGEDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_RESETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_GETDBI_SLAVE_PF0_PORT_LOGIC_GEN4_LANE_MARGINING_2_OFF_RSVDP_29_SETDWC_pcie_wire_cpcie_usp_4x8.csr49012Reserved for future use.30290x0R--31310x0rregisterDBI_Slave.PF0_PORT_LOGIC.PIPE_RELATED_OFFPIPE_RELATED_OFFDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_BYTE_ADDRESSDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_OFFSETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_BYTE_OFFSETDWC_pcie_wire_cpcie_usp_4x8.csr490750x490R/W0x00000022DBI_Slave_PF0_PORT_LOGIC_PIPE_RELATED_OFFPIPE Related Register.This register controls the pipe's capabitity, control, and status parameters.falsefalsefalsefalseRX_MESSAGE_BUS_WRITE_BUFFER_DEPTHDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_MSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_LSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_RESETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_GETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RX_MESSAGE_BUS_WRITE_BUFFER_DEPTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr49033RXMessageBusWriteBufferDepth defined in the PIPE Specification.Indicates the number of write buffer entries that the PHY has implemented to receive writes from the controller.If the value is less than 2 for PIPE 5.1.1 or 1 for PIPE 4.4.1, the controller issues only write_commited commands, never write_uncommitted.Note: This register field is sticky.300x2R/WTX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTHDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_MSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_LSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_RESETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_GETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_TX_MESSAGE_BUS_MIN_WRITE_BUFFER_DEPTH_SETDWC_pcie_wire_cpcie_usp_4x8.csr49047TXMessageBusMinWriteBufferDepth defined in the PIPE Specification.Indicates the minimum number of write buffer entries that the PHY expects the controller to implement to receive writes from it.Note: This register field is sticky.740x2RPIPE_GARBAGE_DATA_MODEDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_MSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_LSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_RESETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_GETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_SETDWC_pcie_wire_cpcie_usp_4x8.csr49066PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received after the electrical idle ordered-set until when any of the following three conditions are true: -- RxValid is deasserted -- a valid RxStartBlock is received at 128b/130b encoding -- a valid COM symbol is received at 8b/10b encodingNote: This register field is sticky.880x0R/WRSVDP_9DBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_WIDTHDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_MSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_LSBDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_RANGEDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_RESETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_FIELD_MASKDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_GETDBI_SLAVE_PF0_PORT_LOGIC_PIPE_RELATED_OFF_RSVDP_9_SETDWC_pcie_wire_cpcie_usp_4x8.csr49074Reserved for future use.3190x000000R
Addressmap Information for 'DWC_pcie_wire_cpcie_usp_4x8'